Siemens Aktiengesellschaft

Dietmar Wanner

Martin Kiesel

Günter Schwesig

Guido Seeger

Oswald Kaesdorf

Hanno Walders

Hendrik Rotsch

Michael Zeitler

Ulrich Hahn

A method for controlled synchronization to an astable clock system, and reception unit corresponding thereto are disclosed. Soft synchronization using a slight change in the period duration of the clock signal produced makes it possible to alter said clock signal such that a phase difference between the stable clock signal produced by a phased locked loop upon a synchronization signal and the clock signal produced for an application is slowly reduced until the two clock signals are in synchronization with one another after a period of time.

Method for controlled synchronization to an astable clock system, and reception unit corresponding thereto

Synchronization of a bus master to a bus slave permits the desired hierarchical structuring of buses by virtue of a bus slave on a bus receiving the synchronization information for an associated bus master is disclosed. A phase locked loop is used to filter this clock information and to regenerate missing clock pulses. This clock which is now 'sound,' is supplied to one or more parallel bus masters of other buses, which generate the corresponding clock information using the necessary messages on the respective bus. This principle is independent of the respective bus system, which means that a plurality of identical buses or else different bus systems can be operated hierarchically in synchronization with one another.

Method for synchronizing a plurality of bus systems, and hierarchical multibus system corresponding thereto

Uniform distribution of a correction determined by a PLL over the subordinate clock signals is undertaken by dividing a phase-regulated value by the number of subordinate clock signals. Division by way of successive addition is performed such that time conflicts with subordinate clock signals generated in real time are successfully avoided despite the required time duration of such a division. The synchronicity can be further raised by also uniformly distributing a division remainder. A particularly effective implementation of this division employs subsequent rounding for real time use.

Device and method for digitally generating equidistant synchronous frequency-multiplied clock pulses

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Erlangen, Germany

Dietmar Wanner