Infineon Technologies Ag

Qimonda Ag

Fraunhofer-ges. Zur Förderung Der Angewandten Forschung E.v.

Dietmar Temmler

Martin Schrems

Martin Popp

Andreas Wich-Glasen

Frank Richter

Wolfram Karcher

Christoph Nölscher

Peter Moll

Herbert Benzinger

J&uuml;rgen Faul

Catharina Pusch

Hans-Peter Moll

Kristin Schupke

Matthias Foerster

Christoph Noelscher

Srivatsa Kundalgurki

Anke Krasemann

Peter Weidner

Rudolf Strasser

Wolfgang Gustin

Uwe Schilling

Barbara Lorenz

Alexander Sieck

Daniel Koehler

Stefan Rongen

Stefan Saager

Jörn Regul

Joerg Wiedemann

Ulrike Gr&uuml;ning-Von Schwerin

Kerstin Pomplun

Karl Heinz K&uuml;sters

Karl Bedrich

The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

Method for producing a structure on the surface of a substrate

A field-effect transistor includes a source region, a drain region and a channel region between the source and the drain region. A gate electrode is also arranged between them, where a lower edge of the gate electrode is formed below a lower edge of at least one of the source and drain regions. A first insulator structure is provided between the gate electrode and the source region. A second insulator structure is provided between the gate electrode and the drain region. The first and the second insulator structures are formed asymmetric and may be adapted to different requirements. The asymmetric approach may provide longer transistor channels, a lower resistance of the gate electrode and smaller footprints for 3D-channel-transistors of, for example, array and support transistors in memory cells or power applications.

3-D channel field-effect transistor, memory cell and integrated circuit

A semiconductor device with a substrate includes a structure. The structure has a first part and a second part. At least one section of the edge of the first part of the structure is at an essential constant distance measured parallel to the substrate to a first section of an edge of a second structure. At least one section of the edge of the second part of the structure is lined with an edge of a second section of the same second section. The first section of the edge of the second structure and a second section of the edge of the second structure merge at least at one point, whereby the angle between the tangents of the edges of the first and second section of the second structure is less than 90&#xb0;. The structure and the second structure are distanced by a spacer structure.

Semiconductor device, method for manufacturing a semiconductor device and mask for manufacturing a semiconductor device

A method for fabricating a trench includes providing a semiconductor substrate made of a semiconductor material. A trench is etched into a surface of the semiconductor substrate such that a trench wall is produced. At least one layer is provided on the trench wall. This step is performed in such a way that the topmost layer provided on the trench wall is constructed from a sealing material. A selective epitaxy method is carried out in such a way that a monocrystalline semiconductor layer is formed on the surface of the semiconductor substrate and preferably no semiconductor material grows directly on the sealing material. A partial trench is etched in a surface of the epitaxially grown semiconductor layer. This step is performed in such a way that at least part of the layer made of the sealing material is uncovered. An uncovered part of the layer made of the sealing material is then removed.

Trench and a trench capacitor and method for forming the same

The invention relates to a trench isolation with a self-aligning surface sealing and a fabrication method for said surface sealing. In this case, the surface sealing may have an overlap region of the substrate surface or a receded region into which extends an electrically conductive layer formed on the substrate surface.

Trench isolation having a self-adjusting surface seal and method for producing one such trench isolation

A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.

Method for filling trench and relief geometries in semiconductor structures

The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling; providing a sacrificial filling on the liner mask layer to completely fill the trench; shallow etching back of the sacrificial filling into the trench; forming a first mask on the top side of the sacrificial filling in the trench; removing a subregion of the sacrificial filling in the trench using the first mask; and optionally removing a subregion of the first liner mask layer below it on the partial filling, the remaining subregion of the sacrificial filling in the trench serving as a second mask.

Method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure

A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substrate with a selectively grown epitaxial layer. The selection transistor is formed in the selectively grown epitaxial layer, comprises a source region connected to the trench capacitor and a drain region connected to a bit line. The junction depth of the source region is chosen so that the source region reaches as far as the insulating covering layer. Optionally, the thickness of the epitaxial layer can be reduced to a thickness by oxidation and a subsequent etching. Afterwards, a contact trench is etched through the source region down to the conductive trench filling, which trench is filled with a conductive contact and electrically connects the conductive trench filling to the source region.

Dram memory cell with a trench capacitor and method for production thereof

The invention relates to a method for determination of the depth of depressions which are formed in a mount substrate. According to the invention, an essentially uniform layer of a wetting agent is applied, which contains depressions, on a surface of the mount substrate, a time profile of the decrease in weight of the mount substrate is recorded, and the recorded time profile of the decrease in weight of the mount substrate is evaluated. The invention also relates to a measurement apparatus.

Method and apparatus for determination of the depth of depressions which are formed in a mount substrate

The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow Ican be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current I. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

Field effect transistor and method for fabricating it

To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.

Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor

A semiconductor memory cell is formed in a substrate and includes a trench capacitor and a selection transistor. The trench capacitor includes a capacitor dielectric and a conductive trench filling. Disposed on the conductive trench filling is a diffusion barrier on which an epitaxial layer is formed. The selection transistor is disposed as a planar transistor above the trench capacitor. A drain doping region of the selection transistor is disposed in the epitaxial layer.

Semiconductor memory cell with trench capacitor and selection transistor and method for fabricating it

A memory cell has a trench capacitor, in which the area required over a terminal area of the trench capacitor is advantageously reduced by the formation of a particularly thin insulation collar. The insulation collar is reduced to such an extent that although a lateral current is prevented, the formation of a parasitic field-effect transistor is permitted. In order that, however, overall no current flows via the parasitic field-effect transistor, a second parasitic field-effect transistor is disposed in a manner connected in series, but is not turned on. This is achieved by the formation of a thicker second insulation collar that isolates the filling of the trench capacitor from the surrounding substrate.

Memory cell having a thin insulation collar and memory module

The instant invention is a method for fabricating a trench contact to a deep trench capacitor with a polysilicon filling in a trench hole formed in a silicon substrate. An epitaxy process is performed to selectively grow silicon above the polysilicon filling in the trench hole. An opening leading to the polysilicon filling is anisotropically etched into the epitaxially grown silicon. The opening has lateral dimensions that are smaller than those of the polysilicon filling, and the opening is filled with polysilicon.

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Dresden, Germany

Dietmar Temmler