International Business Machines Corporation

Dietmar Schmunkamp

Tobias Webel

Patrick James Meaney

Markus Kaltenbach

Scott Barnett Swaney

Timothy Gerard McNamara

Johannes C Reichart

Ulrich Weiss

Simon H Friedmann

Walter Niklaus

Thomas E Gilbert

Karin Rebmann

Steven Michael Douskey

Martin Ohmacht

Erich Klink

Wilhelm Ernst Haller

Krishnan Sugavanam

Hubert Harrer

Roland Frech

Klaus J Getzlaff

Andreas Wagner

Rudolf Adriaan Haring

Helmut H Weber

Bernd Leppla

Ralph E Bellofatto

Bernd Garben

Ching-Lung L Tong

Ralf Ludewig

Peter Rudolph

Guenter Knauft

Adolf Martens

Moyra Kathleen McManus

Halim S Tandjung

Thomas Pfluger

Stefan Korner

Bryan J Weatherford

Robert Braun

Klaus D Muller

A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.

Translation lookaside buffer purging with concurrent cache updates

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Testing and operating a multiprocessor chip with processor redundancy

A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Multi nodal computer system and method for handling check stops in the multi nodal computer system

A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.

Method and apparatus for automatic scan completion in the event of a system checkstop

A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.

Method to prevent firmware defects from disturbing logic clocks to improve system reliability

The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) () and the wiring () from there to multiple, PLL-() free clock chips () is provided. Instead of only one DCSC () and one single wiring (), two of them (----) are used combined with a further particular logic present on each clock chip (), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.

Redundant oscillator distribution in a multi-processor server system

Processing system having improved bi-directional serial clock

Method for reducing a transient thermal mismatch

An electrical circuit for generating clock pulses for a multi-chip computer system which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clock splitter circuit is provided on the clock generation circuit. This clock splitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clock splitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clock splitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.

Electrical circuit for generating pulse strings

A clock generator system is provided which includes several clock generators each containing a feedback shift register. A parity bit is calculated over the output of all shift registers and compared to an expected value. Additionally, a parity bit is calculated for each shift register, over the bits stored in the shift register, the number of ONE bits in a shift register being constant. A parity error at the output of the shift registers in combination with an error in the additional parity bit allows the correction of the erroneous clock pulse generated by the shift register in error.

Parity-checked clock generator system

Growing community of inventors

Schoenaich, Germany

Dietmar Schmunkamp