Synopsys, Inc.

Ericsson Ab

Dietmar Petras

Thomas M Philipp

Matthias Spycher

Tom Michiels

Niels Vanspauwen

Rainer Leupers

Jan M J Janssen

Thorsten H Grötker

Khaled Fazel

Christoph Schumacher

Stephan Tobies

Volker Engels

Koen M C Velle

Kristof A Niederholtmeyer

Embodiments of the present disclosure support a simulation of a plurality of processor core models. The processor core models are executed in parallel within a sliding time window of a defined size. Each processor core model is executed in a different corresponding thread and advances a local core time within the sliding time window. The sliding time window advances by updating a start time of the sliding time window based on the local core time of each processor core model. One or more hardware models and a simulation kernel are executed in a separate thread having a simulation time and simulation events. The start time of the sliding time window is updated based further on an event time of a next event of the simulation events scheduled in the separate thread.

Sliding time window control mechanism for parallel execution of multiple processor core models in a virtual platform simulation

A system and method of debugging a multi-threaded process with at least one running thread and at least one suspended thread is disclosed. Embodiments utilize a blocking function to block the thread of a process while other threads are allowed to run. The blocking function may be executed in a suspended thread by a debugger under control of a thread blocking controller. The other threads may implement interprocess communication channels for enabling communication between the process and another application. A simulated user interface (UI) of a debugger enables interaction with users while a hardware simulation thread is blocked, where blocking of the hardware simulation thread may be implemented by a thread blocking component implemented externally to the debugger. Where a thread blocking controller is implemented within the debugger, a debugger UI may interact with a user while the hardware simulation thread is blocked and interprocess communication threads are running.

System and method of debugging multi-threaded processes

A system for simulating hardware is disclosed wherein stopping the simulating for investigating a state of the simulating is constrained to occur at points of simulation synchronization. A delta cycle may be inserted into a simulation to provide a point of simulation synchronization. The delta cycle may be inserted at the beginning of a simulation loop.

System and method for stopping integrated circuit simulation

Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Direct memory interface access in a multi-thread safe system level modeling simulation

A simulation environment, in one embodiment, includes a debugger server, one or more debuggers, and one or more debugger adapters. Each debugger adapter couples a corresponding debugger to the debugger server. The debugger server coordinates the run mode of the debugger adapters. Each debugger adapter controls the run mode of its corresponding debugger.

Coordinating and controlling debuggers in a simulation environment

An ISS (instruction set simulator) debugging method. The method includes executing a plurality of instructions of an ISS (instruction set simulator). For each instruction, an ISS simulation state is synchronized to a simulation time when the execution of the instruction is finished. At least two debugger components are executed in conjunction with the execution of the ISS, wherein the debugger components are each coupled to control the ISS.

Method and system for instruction set simulation with concurrent attachment of multiple debuggers

Simulation control techniques include shutting down peer processes and user code modules, storing an image of a simulation as a checkpoint after the peer processes and user code modules are shutdown, and re-starting user code modules and peer processes after storing an image of the simulation. The resulting checkpoint and processes can be used for restoring from a checkpoint or restarting a new simulation environments having peer processes such as debuggers coupled to the simulation.

Simulation control techniques

A simulation environment, in one embodiment, includes a debugger server, one or more debuggers and one or more debugger adapters. Each debugger adapter couples a corresponding debugger to the debugger server. The debugger server coordinates the run mode of the debugger adapters. Each debugger adapter controls the run mode of its corresponding debugger.

Techniques for coordinating and controlling debuggers in a simulation environment

For communicating data on a transmission channel () between a central station (BS) and a plurality of subscriber stations (M), for each transmission connection between the central station (BS) and a specific subscriber station (M), a method for coding and/or modulating the payload to be transmitted is selected among a plurality of methods supported by the central station (BS) and the specific subscriber station (M). To this end, the load of the transmission channel () is detected, and the selection is carried out taking account of the detected load.

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Langerwehe, Germany

Dietmar Petras