Ihp Gmbh-innovations for High Performance Microelectronics/leibniz-institut Fur Innovative Mikroelektronik

Ihp Gmbh Innovations for High Performance Microelectronics/leibniz Institut for Innovative Mikroelektronik

Dietmar Kissinger

Alexey Balashov

Iria Garcia Lopez

Herman Jalli Ng

Ahmed Awny

Pedro Rito

Minsu Ko

Mohamed Eissa

The invention relates to a gain-control stage () for generating gain-control signals (V, V) for controlling an external variable-gain amplifying unit (). The gain-control stage comprises a first () and a second differential amplifier unit () that receive, at a respective input interface () a reference voltage signal (V) and a variable gain-control voltage signal (V). The second differential amplifier unit is configured to provide, via a second output interface (), a control voltage signal (V) to a controllable first current source () of the first differential amplifier unit (). The first differential amplifier unit () is configured to provide, via a first output interface (), the first and the second gain-control signal (V, V) in dependence on the variable gain-control voltage signal (V), the reference voltage signal (V) and a first biasing current (I) that depends on the control voltage signal.

Gain-control stage for a variable gain amplifier

Novel phase locked loop architectures that can overcome the limitation of the maximum operating frequency of the fractional-N phase-locked loop (PLL) for fast-chirp frequency modulated continuous wave (FMCW) radars are suggested. Several phase frequency detector and charge pumps (PFD&CPs) are put in parallel and are operated with reference signals that are generated by using a delay-locked loop (DLL) instead of further increasing the operating frequency of the PFD&CP. The proposed DLL supported parallel PLL architectures enable further speeding up the FMCW chirp as well as improving its linearity and the performance of Range Doppler Radars based on fast-chirp FMCW radar. Methods for operating the parallel fractional N phase locked loop are proposed.

Parallel fractional-N phase locked loop circuit

The invention relates to an amplification circuit (), comprising: a VGA (), an AGC loop () for automatically controlling the gain of the VGA (), a switching circuit () for switching between an AGC mode, in which the gain of the VGA () is automatically controlled by an output signal of the AGC loop () and a manual gain control, MGC, mode, in which the gain of the VGA () can be manually controlled by an input signal, and a read/write circuit () with a contact () for connection to a peripheral system, wherein the read/write circuit () is configured, in the MGC mode, to provide the input signal from the contact () via a write-mode path () to the VGA (), and, in the AGC mode, to provide the output signal of the AGC loop () via a read-mode path () on the contact ().

Amplification circuit with read/write circuit

Growing community of inventors

Frankfurt-am-Main, Germany

Dietmar Kissinger