Sharp Microelectronics Technology, Inc.

Sharp Kabushiki Kaisha Corporation

Other

Dieter W Spaderna

Raed Sabha

Michael F Roberts

Jeffrey L Miller

A System On Chip (SOC) has been provided which includes a crossbar switch between 64 functional I/Os internal to the chip, and 40 external connection pins. The crossbar switch permits a signal at any of the 64 functional I/Os to appear at any of the connector pins. The cross bar switch, permitting signals at the 40 connector pins to appear at any of the 64 specified functional I/Os. Because the switching is done with 4-way switches, the total number of hierarchical switch layers is reduced to 3. A parallel, opposite oriented, network of switches permits input signals delivered to the physical I/Os to be switched to any of the 64 functional I/Os. The small number of switch layers permit connections to be made with a minimum of delay across the switch. A method corresponding to the above-described crossbar switch system is also provided.

System on chip (SOC) four-way switch crossbar system and method

A testing and diagnostic mechanism includes an external bus master allows access of virtually all internal registers on an integrated circuit, and allows the on-chip SRAM/DRAM controllers to access external memory.

Testing and diagnostic mechanism

A multimode cache structure includes a predefined block of memory and controls for that block of memory which allow the memory block to perform multiple functions. The selectable, multiple functions include a cache mode, a SRAM mode, a flush mode and an invalidate mode. A control register is defined and is associated with the predefined memory block, which control register includes multiple status bits therein. Each of the status bits corresponds to one of the multiple functions and, when a particular status bit is set, the predefined block of memory performs a function corresponding to the status bit that is set.

Multi-mode cache structure

An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memory cells are accessed for read or write operations in another array. Also, all the cells in a row of the other array may be precharged as the memory cells in the one array are accessed independently for read or write operations. Accesses to memory cells in addressed rows alternate from one array to another so that the signal conditioning of the memory cells in one array can take place before access in needed and while memory cells are being accessed in another array. Improved status logic unambigously designates the conditions of empty, half full and full, independent of the sequence of data read and write operations. Data signal driver circuitry controls the rate of change of data output signals for improved noise performance and compatibility with external circuitry.

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Aloha, OR, United States of America

Dieter W Spaderna