Robert Boschgmbh

Dieter Thoss

Andreas-Juergen Rohatschek

Thorsten Huck

Stoyan Todorov

Andreas Merker

Eberhard Boehl

Thomas Wagner

Stephen Schmitt

Ruben Bartholomae

Andreas Hempel

Bernd Mueller

Axel Aue

Bernd Lutz

Carsten Gebauer

Bernd Becker

Juergen Hanisch

Achim Schaefer

Uwe Scheurer

Jens Gladigau

Martin Gruenewald

Bernhard Mader

Thomas Lindenkreuz

Jaroslaw Topp

Christian Haubelt

Matthias Knauss

Margit Mueller

Leonardo Luiz Ecco

Thomas Hartgen

Bernard Pawlok

Markus Ferch

Michael Frischke

Rolf Kurrer

Michael Ebert

Athanasios Hailas

Daniel Drescher

Christine Rossa

Alexander Biewer

A method for accessing a data block, stored in a memory unit of a computing unit, of a number of data blocks. The method includes: activating a safe operating mode of the computing unit; in the safe operating mode of the computing unit, accessing the data block; if the access is a read access, reading data from the data block and subsequently writing the data into the data block; if the access includes a write access, reading first data from the data block, removing the first data from a check value associated with the data block, writing second data into the data block, adding the second data to the check value associated with the data block; and checking the check value associated with the data block.

Method for accessing a data block, stored in a memory unit of a computing unit, of a number of data blocks

A method for checking data in a storage unit of a system on a chip; a monitoring unit, which may be activated or deactivated by the system on a chip, being implemented in the system on a chip. When it is activated, the monitoring unit storing error correction codes for executing error correction methods, in the storage unit, such that, for a predefined number of data blocks of the storage unit, in each instance, a data block including an associated error correction code is stored. When access to data in the storage unit is intended to take place, the monitoring unit addresses the respective data and an associated error correction code and checks the addressed data prior to the respective access, using the addressed error correction code, and correcting them when required.

Method and monitoring unit for checking data in a storage unit or a system on a chip

A control device for a motor vehicle, the control device including at least two processor cores and a global memory, each processor core respectively including a local memory and each processor core being set up to access only its own local memory and being set up to access neither the local memories of the other processor cores nor the global memory, a coordination unit being set up to read in data from the global memory of the control device and to write it to the local memories of the individual processor cores, and to read in data from the local memories of the individual processor cores and to write it to the global memory and/or to the local memory of the other processor cores.

Control device for a motor vehicle

A method for operating a control unit of a motor vehicle. A status inquiry is transmitted by a watchdog unit to a first monitoring unit, which is implemented on a first processor core of a multicore processor. A status response is ascertained by the first monitoring unit as a function of the status inquiry. A fault is ascertained by the watchdog unit as a function of the status response.

Method for operating a control unit

In a communications assembly having multiple users, one user is designated as a master and additional users are designated as peripheral modules, at least two of the peripheral modules as well as at least two interface modules are integrated into a shared physical implementation unit, and at least one interface module, which is designated as a slave, is unambiguously assigned to each of the at least two peripheral modules.

Communications assembly having logic multichannel communication via a physical transmission path for serial interchip data transmission

A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.

Method and circuit configuration for determining position minus time

A method for transmitting frames containing data between users of a ring-shaped communication system which has a master and at least one slave as users. Each user has at least one interrupt register, and one field of the at least one interrupt register is associated with an interrupt request and includes a value for an interrupt bit. An interrupt request which includes the interrupt bit is transmitted to the master by a slave in a frame designed as an empty frame. In addition, the empty frame has a toggle bit for all slaves which indicates the state of an interrupt request.

Method for operating a communication system

A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Circuit arrangement for a data processing system and method for data processing

A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Modular structure for processing data

A method is described for transmitting data between participants of a serial, ring-shaped communications arrangement in which the participants are serially connected to one another, wherein a data packet is passed from a participant provided as a master to further participants provided as slaves, wherein the data packet is passed from slave to slave, and wherein address information of the data packet is altered by each slave.

Method for transmitting data

A method is described for monitoring a data memory in which an error detection method is used to detect and/or correct incorrect data words stored in memory lines of the data memory, an address of the data memory at which a data word evaluated as incorrect by the error detection method is stored being written to an auxiliary memory and being made available to a checking program.

Method for monitoring a data memory

A method for evaluating an analog signal of an inductive sensor that carries data on a rotational motion includes directly connecting the inductive sensor to an A-D converter via resistors, and reading in the analog signal by the A-D converter to emit digital data. The digital data is evaluated to determine zero crossings of the analog signal.

Method for evaluating an analog signal by evaluating digital data corresponding to the analog signal to determine zero crossings of the analog signal

A communication system configuration has an annular design and includes multiple participants which are serially interconnected, one participant being configured as a master and the remaining participants being configured as slaves. The master is configured for transmitting a data packet to one or a plurality of slaves, and each slave has a shift register. The communication system includes a participant which has an external interface and is adapted for receiving data via the external interface from outside of the communication system to implement a debugging or a programming of one or a plurality of participants of the communication system or for transmitting data to outside of the communication system.

Communication configuration and method for debugging, respectively for programming one or more participants of the communication configuration

A circuit configuration for driving an electric motor includes a signal evaluation module, which stores a number of output patterns. An input pattern is specified, and as a function of the input pattern, one of the output patterns is output, by which the electric motor is driven.

Method for driving an electric motor

A memory protection unit includes at least a first access control unit and a second access control unit programmed for controlling an access to a memory device. Further a method to operate a processing system comprising multiple processing devices and multiple memory protection units associated to the multiple processing devices. The access to the memory by a processing device is approved if first access control unit and second access control unit of the memory protection associated to the processing device approves the access and access is rejected if first access control unit or second access control unit rejects the access. The first access control unit is programmable by the associated processing device alone and the programming of the second access control unit is readable by an additional processing device which is to be used in a system with multiple programming devices, not the associate processing device.

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Schwieberdingen, Germany

Dieter Thoss