Other

Infineon Technologies Richmond, LP

Dieter Rathei

Joerg Wohlfahrt

Thomas Hladschik

Michael Bernhard Sommer

Joerg W Wohlfahrt

Ulrich Zimmermann

Robert Petter

Mark E Luzar

Peter Oswald

Babatunde Ashiru

Jens Holzhaeuser

Thomas S Taylor

Luis G Andrade

Thomas Giegold

A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A measurement closest to the storage percentile is stored.

Method of monitoring a semiconductor manufacturing trend

A method of monitoring trends in semiconductor processes is provided. Lot values are assigned to each of a set of wafer lots prior to performing semiconductor processes. After at least some of the semiconductor processes, at least some of the wafer lots are tested to generate a set of test data. A degree of scrambling is calculated for the set of wafer lots already tested using the test data: calculating a current scrambling value by subtracting the lot value of a current wafer lot from a maximum lot value of the lot values assigned for the set of wafer lots to yield the current scrambling value; storing the current scrambling value into a set of scrambling values; and determining a current adjusted maximum scrambling value by multiplying a selected multiplier value with a current maximum scrambling value of the set of scrambling values for a selected number of wafer lots.

A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A number of spatial regions on the wafer is designated. A first group of measurements from the set of measurements is obtained for a first spatial region of the spatial regions. A measurement closest to the storage percentile is stored.

A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.

Method of and system for analyzing cells of a memory device

A method for classifying patterns of failcodes on a semiconductor wafer, in accordance with the present invention, includes determining failcodes for chips on the wafer and checking adjacent chips for each chip on the wafer having a failcode to determine a failcode pattern having a defined number of chips.

Method and apparatus for fast automated failure classification for semiconductor wafers

A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating the test sequence limited yield loss for each of the wafers, and apportioning the test sequence limited yield loss to selected ones of the test based upon the absolute or cumulative number of fails identified by the tests of the test sequence. In some embodiments, core parametric test data is correlated with the test sequence limited yield and analyzed to determine reparability.

Method for semiconductor yield loss calculation

The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a memory chip. The method defines a group of characteristics for a semiconductor of given dimensions. The method defines a ratio based on variables supplied by production test systems. By comparing a set of characteristics for a specific semiconductor to the ratio to determine the dominant type of failure on the semiconductor chip. The invention is an efficient method of obtaining information regarding the types of failures common on semiconductor chips.

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Graz, Austria

Dieter Rathei