Institut Fuer Halbleiterphysik Frankfurt (oder) Gmbh

Ihp Gmbh-innovations for High Performance Microelectronics/leibniz-institut Fur Innovative Mikroelektronik

Ihp Gmbh-innovations for High Performance Microelectronics/institut Fur Innovative Mikroelektronik

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Ihp Gmbh - Innovations for High Performance Microelectronics

Institut Fuer Halbleiterphysik Franfurt (oder) Gmbh

Ihp-gmbh—innovations for High Performance Microelectronics/leibniz-institut Fur Innovativ Mikroelektronik

Ihp Gmbh - Innovations for High Performance Microelectronic / Institut Fur Innovative Mikroelektronik

Ihp Gmbh-innovations for High Performance Microelectronics/institute for Innovative Mikroele

Dieter Knoll

Bernd Heinemann

Karl-Ernst Ehwald

Bernd Tillack

Wolfgang Winkler

Dirk Wolansky

Stefan Lischke

Rudolf Ehwald

Holger Rücker

Lars Zimmermann

Alexander Fox

Yuji Yamamoto

Steffen Marschmayer

Andreas Trusch

Peter Schley

Katrin Blum

Henning Zinke

Juergen Drews

Eberhard Bugiel

A diode is described which comprises a light-sensitive germanium region () located on a waveguide () made of silicon or silicon germanium and which has lateral dimensions in a direction transverse to a direction of light propagation in the waveguide that are identical or at most 20 nm per side shorter in comparison with the waveguide.

High-speed germanium PIN photodiode

A diode comprising a light-sensitive germanium region which is totally embedded in silicon and forms with the silicon a lower interface and lateral interfaces, wherein the lateral interfaces do not extend perpendicularly, but obliquely to the lower interface and therefore produce a faceted form.

Germainium pin photodiode for integration into a CMOS or BICMOS technology

A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other.

Complementary bipolar semiconductor device

The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate () with one or more buried high-carbon Si layers () under an epitaxial layer and with the Si cap layer (), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.

Layers in substrate wafers

The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an associated base connection region. The collector and the collector contact region are formed in the same active region. In addition the base connection region extends partially over the active region and is separated from the surface of the active region by an insulator layer.

Semiconductor device and method for production thereof

The invention concerns a bipolar transistor with an epitaxially grown base and a self-positioned emitter, whereby the base is formed from a first substantially monocrystalline epitaxial region () which is arranged in parallel relationship to the surface of the semiconductor substrate () and a second substantially polycrystalline and highly doped region () of the same conductivity type which is arranged in perpendicular relationship to the substrate surface and encloses the first region at all sides and that said second region, at least at one side but preferably at all four sides, is conductingly connected to a third, preferably highly doped or metallically conducting, high temperature-resistant polycrystalline layer () which is arranged in parallel relationship to the surface of the semiconductor substrate and forms or includes the outer base contact to a metallic conductor track system.

BiCMOS structure, method for producing the same and bipolar transistor for a BiCMOS structure

An apparatus for measuring the viscosity of a fluid having a first rigid member extending from a body of semiconductor material and provided with a first conductive path and a second resiliently flexible member provided with a second conductive path and arranged in cantilever fashion over the rigid member. At least one of the conductive paths may be selectively energized to brig about relative movement between the rigid and flexible member. Subsequent deenergization of the path causes the resiliently flexible member to return to its initial position, the rate of return being measured to derive a signal representative of the viscosity. Also described are methods of carrying out the measurement and of fabricating the apparatus.

Method and apparatus for measuring viscosity

The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.

Method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip

A CMOS-compatible DMOS transistor can be designed by virtue of a suitable layout configuration optionally for very high drain voltages or for power amplification at very high frequencies and which can be produced at a low level of additional cost in comparison with a conventional sub-&#x3bc;m production technology for CMOS circuits. A gate insulator of the transistor is of a unitary thickness under a control gate in the entire (active) region through which current flows. A zone of increased doping concentration (well region) which is near the surface and which determines the transistor threshold voltage is so arranged under the control gate that it occupies the entire area under the control gate which is on the active region and ends within a so-called drift space between the control gate and a highly doped drain region. The entire surface of the drift space is covered by a zone of the conductivity type of the drain region (VLDD), which is lowly doped in comparison with the highly doped drain region.

Cmos-compatible lateral dmos transistor and method for producing such a transistor

The aim of the invention is to provide for a bipolar transistor and a method for producing the same. Said bipolar transistor should have minimal base-emitter capacities and very good high frequency characteristics. The static characteristics, especially the base current ideality and the low frequency noise, of a bipolar transistor with weakly doped cap layer ( ) should not significantly deteriorate and process complexity should not increase. According to the invention, the problem is solved by inserting a special doping profile in a cap layer ( ) (cap doping) which has been produced epitaxially. A minimal base emitter capacity and very good high frequency characteristics can be obtained by means of said doping profile. At the same time, the efficiency of the generation/recombination active boundary surface between the cap layer ( ) and the isolator ( ) in the polysilicon overlapping area in the relevant working area of the transistor is reduced and the base current ideality is improved. The section at the base side in the cap layer ( ) has a preferred thickness of between 20 nm and 70 nm and is only doped weakly, preferably less than 5&middot;10 cm . Said section is crucial for the good high frequency characteristics.

Bipolar transistor and method for producing same

The invention relates to a bipolar transistor and a method for producing same. The aim of the invention is to provide a bipolar transistor and a method for producing same, which during the use of a single-process poly-silicon technology with differential epitaxis for the production of bases overcomes the disadvantages of conventional systems, so as notably further to improve the high-speed properties of a bipolar transistor, provide the most conductive connections possible between the metal contacts and the active (internal) transistor region as well as a minimized passive transistor surface, while at the same time avoiding greater process complexity and increased contact resistances. To this end a surface relief is produced in the active emitter region by a wet-chemical process. A single-process poly-silicon bipolar transistor having a base produced by epitaxis in accordance with the invention permits a reduction in external base resistance without causing a deterioration in emitter properties. Because the internal and external base regions are deposited continuously no interface problems arise during connection of the base. Base-collector capacity can also be lowered.

The invention relates to a vertical bipolar transistor and a method for the production thereof. The aim of the invention is to produce a vertical bipolar transistor and to disclose a method for the production thereof, whereby excellent high frequency properties can be obtained for said transistor using the simplest possible production technology involving an implanted epitaxy-free collector and only one polysilicon layer spread over a large surface and which can be easily integrated into a conventional mainstream CMOS process without epitaxially produced trough areas. It is possible to simplify technology, while at the same time improving the high frequency parameters of vertical bipolar transistors by reducing the parasitic lateral and vertical components of the resistance of the collector, by means of a self-adjusting transistor construction in conjunction with a special method of production, whereby a highly doped monocyrstalline base connection area surrounding the active base in a ring-like manner is removed in the region of the collector connection by reactive ion etching, together with the underlying less doped area of the collector or a part thereof.

Vertical bipolar transistor

This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.

Growing community of inventors

Frankfurt-am-Main, Germany

Dieter Knoll