Semiconductor Components Industries, LLC

Dieter Jozef Joos

Johan Camiel Julia Janssens

Philippe Debosque

Jorg Jos Daniels

Philippe Quarmeau

Yves Renard

Thomas Sevrin

David Pierre Jean Robert Levacq

Patrick Lepers

Power monitors, power supply circuits, and methods for operating a power supply. The method includes determining a voltage of a power rail provided to a load device from the power supply. The method also includes detecting that the voltage of the power rail is greater than or equal to an over-voltage threshold. The method further includes incrementing an over-voltage counter when the voltage of the power rail is detected as being greater than or equal to the over-voltage threshold. The method also includes detecting that the over-voltage counter is equal to a threshold value. The method further includes generating an interrupt signal when the over-voltage counter is detected as being equal to the threshold value.

Diagnosing power rail over-voltage and under-voltage conditions

In some aspects, a power supply system includes a plurality of power supply devices configured to be connected to an integrated circuit, where a power supply device of the plurality of power supply devices includes a voltage regulator configured to generate a rail voltage, and an internal diagnostic circuit. The internal diagnostic circuit is configured to detect activation of an enable signal to activate the plurality of power supply devices according to an activation power sequence, detect a rail violation of the activation power sequence in response to a value of the rail voltage at a first time, not satisfying a first condition defined by a voltage threshold, or at a second time, not satisfying a second condition defined by the voltage threshold. In response to the rail violation being detected, the internal diagnostic circuit is configured to activate an interrupt signal.

Power supply system for detecting a rail violation in a multi-rail sequence

Devices, systems and methods for monitoring interconnect lines may include operations for transmitting, by a transmit block to a receive block, a first signal over a first interconnect line; executing, by the transmit block, a first transmit logic operation on the first signal with respect to a second signal, on at least one second interconnect line to generate a transmit signal; receiving, by the transmit block, a receive signal resulting from a receive logic operation executed by the receive block on a received first signal on the first interconnect line with respect to a received second signal received on at least one second interconnect line; executing, by the transmit block, a second transmit logic operation on the transmit signal with respect to the receive signal; and generating, by the transmit block and based on the executing of the second transmit logic operation, a result signal.

Monitoring of interconnect lines

The various embodiments of the present disclosure are directed to devices, systems and methods for mitigating fault propagation between two or more safety components. A system, for avoiding propagation of a fault between two or more safety components may include a control unit outputting an input signal, a first safety component electrically coupled to receive the input signal from the control unit; a second safety component electrically coupled to receive the input signal from the control unit; and a first isolating component electrically disposed between and further coupling the control unit with the first safety component. Each of the first safety component and the second safety component are electrically coupled to the control unit by at least a common lead. The first isolating component prevents a first IC fault arising with respect to the first safety component from propagating, via the input signal, to the second safety component.

Devices, systems and methods for avoiding fault propagation in safety systems

In embodiment, a measurement circuit forms a compensation signal that is representative of disturbances that are received while the measurement circuit is not receiving a signal to be measured, then the circuit removes the compensation signal from the measurement signal before measuring the value of the measurement signal.

Measurement circuit and method therefor

In an embodiment, a differential buffer may include a first input stage that compares a non-inverting portion of an input signal alternately to a non-inverting portion of an output and to an inverting portion of the output. Another embodiment of the differential buffer may also include a second input stage that compares the inverting portion of the input signal alternately to the inverting portion of the output signal and to the non-inverting portion of the output signal. Other embodiments of the differential buffer may include a feedback chopper switch that transfers the non-inverting portion of the output signal and the inverting portion of the output signal to the first input stage and to the second input stage.

Method of forming a semiconductor device and structure therefor

In one form, a spread spectrum clock generator includes an oscillator and a digital modulator. The oscillator has a control input for setting an output frequency, and an output for providing a clock output signal. The digital modulator is responsive to the clock output signal to provide a control code to the control input of the oscillator as a periodic signal with a plurality of discrete steps, wherein the digital modulator provides said control code at each of said plurality of discrete steps for substantially a predetermined time.

Spread spectrum clock generator and method

An illustrative converter embodiment employs an oscillator comprising a capacitor and a comparator. The capacitor is alternately coupled to a charging current source and a discharging current source, the charging current source operating to charge the capacitor at a first rate and the discharging source operating to discharge the capacitor at a second rate. The comparator asserts an output signal when the capacitor charges to a first threshold voltage and deasserts the output signal when the capacitor discharges to a second threshold voltage. The first rate may be proportional to the input voltage and the second rate may be fixed. The output signal may be applied to the gate of a transistor to alternately apply the input voltage across an inductor and to apply current from the inductor to a capacitance. The duty cycle of the output signal is inversely proportional to the input voltage, or at least approximately so.

Area-friendly method for providing duty cycle inverse to supply voltage

Various disclosed leakage compensation apparatus and methods enable HV MOS transistors to be employed for ultralow current operation. One illustrative embodiment is a backup energy block that includes: a pair of input terminals that couple to a backup energy source; an anti-series switch that supplies power from the pair of input terminals to a voltage regulator (when closed) and isolates power from the pair of input terminals to the voltage regulator (when open); a control current source; and an HV MOS control transistor that selectively couples the control current source to a control signal line to open and close the anti-series switch; and a compensation current source coupled to the control signal line to provide a compensation current matched to a parasitic leakage current from the control transistor. The compensation current source includes an HV MOS compensation transistor matched to the control transistor.

Growing community of inventors

Nieuwenrode, Belgium

Dieter Jozef Joos