U.S. Philips Corporation

Dieter J Janta

Winfried B Jansen

Burkhard Dick

Wolfgang Nolde

A current mirror arrangement including an input current path comprising a main current path of a first current mirror transistor and a transistor connected thereto in a cascode configuration and referred to as first cascode transistor, an output current path comprising a main current path of a second current mirror transistor and a transistor connected thereto in a cascode configuration and referred to as second cascode transistor, the current mirror transistors being interconnected in a current mirror configuration and their control terminals being connected to a first circuit point, the connected control terminals of the cascode transistors being interconnected and being connected to an input terminal in the input current path of the current mirror arrangement, the input terminal being constituted by a terminal of the main current path of the first cascode transistor, and an output terminal being constituted by a terminal of the main current path of the second cascode transistor, and a current splitting circuit for deriving a part of a current from the first circuit point in the output terminal, the current splitting circuit is adapted to split up the current from the first circuit point directly to the output terminal and a reference point.

Current mirror arrangement

A phase comparison circuit includes a double balanced mixer stage which receives a sine signal as well as this sine signal in anti-phase and a square-wave switching signal of the same nominal frequency, two active current mirror circuits are used which incorporate at least two common negative feedback circuit elements, the first of which is operative in the input-sided negative feedback of the first current mirror circuit and in the output-sided negative feedback of the second current mirror circuit and the second of which is operative in the reverse way. The two current mirror circuits are alternately connected to the two balanced mixer stages by means of a switching stage during the half cycle clock of the switching signal.

Phase comparison circuit

The invention relates to the synchronization of a frequency-controllable oscillator in a PLL circuit with a carrier. The adjustment of this oscillator to the carrier frequency can be dispensed with in that additionally a frequency discriminator is provided which initially tunes the oscillator in accordance with the frequency difference. The frequency discriminator compares each oscillator frequency with a stable reference frequency which is proximate to the desired frequency and tunes the oscillator until it is in the range of the reference frequency. Subsequently the frequency discriminator is blocked and the further synchronization is taken over by the phase discriminator in the PLL circuit.

Circuit arrangement for synchronizing a frequency-controllable oscillator

A demodulator circuit for demodulating a signal which varies substantially sinusoidally with time, such as a stereo signal having a carrier frequency, comprises a mixer circuit having a first input with a linear transfer characteristic which receives the stereo multiplex signal u.sub.m to be demodulated and having a second input with a substantially hyperbolic tangent transfer characteristic, the second input receiving a signal u.sub.d. The signal u.sub.d is a voltage having a triangular wave shape superimposed with the triangular wave shape having the carrier frequency. A stereo output signal L and R is produced having minimal third and fifth harmonics of the carrier frequency is produced from a matrix circuit as a result of the triangular shape and amplitude of the signal u.sub.d.

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Hamburg, Germany

Dieter J Janta