Infineon Technologies Ag

Siemens Aktiengesellschaft

Dieter H&auml;rle

Patrick Heyne

Thoralf Gr&auml;tz

Bret A Johnson

Helmut Schneider

Martin Buck

Thoralf Gra&euml;tz

The optimized-delay multiplexer includes at least two pass elements that are respectively driven via a first path by a control signal directly, and via a second path by the control signal inverted by an inverter. A further pass element is connected in the first path to simulate the delay caused by the inverter. As a result, the at least two pass elements are switched simultaneously.

Optimized-delay multiplexer

A configuration for testing a plurality of memory chips on a wafer, in which needles are used to supply the memory chips with supply voltages, an initialization signal, a read signal, a clock signal as well as address, data and control signals. The address, data and control signals are in this case produced by a logic device disposed in an edge area of the memory chip and are supplied directly to the memory chips.

Configuration for testing a plurality of memory chips on a wafer

The integrated circuit has two inputs each supplying one input clock. Two outputs each output one output clock. The first logic levels of the output clock signals at the outputs do not overlap in time.

Integrated circuit for producing two output clock signals at levels which do not overlap in time

The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a first output terminal. The input signal is also routed on a second path, connected in parallel with the first path, via an inverter, and to a second output terminal. The first and the second output terminal are connected to a first and a second output node, respectively, via a compensation device. The compensation device compensates for the different time delays in the signals on the first and on the second path.

Circuit configuration for producing complementary signals

A dynamic memory includes memory cells combined to form blocks and blocks combined to form at least one block group. The memory also includes bit lines and word lines connected to the memory cells for selecting the memory cells, redundant memory cells within the blocks, at least one redundant word line in at least one of the blocks, and a decoder unit connected to the word lines. The redundant word lines are connected to the redundant memory cells for selecting the redundant memory cells. A redundant word line, after redundancy programming has been carried out, selectively replaces a word line in any of the blocks. In a first mode of operation, no more than one of the word lines is selected simultaneously per block group. In a second mode of operation, more than one of the word lines is selected simultaneously per block group, and redundancy programming is deactivated.

Growing community of inventors

München, Germany

Dieter Härle

Growing community of inventors

München, Germany

Dieter H&auml;rle

Dieter Härle