International Business Machines Corporation

Globalfoundries Inc.

Dieter F Wendel

Juergen Pille

James Douglas Warnock

Rolf Sautter

Jens Leenstra

Alexander Fritsch

Sang Hoo Dhong

Joel Abraham Silberman

Osamu Takahashi

Otto Andreas Torreiter

Effendi Leobandung

George McNeil Lattimore

Michael B Kugel

Amira Rozenfeld

Friedrich-Christian Wernicke

Tobias Werner

Albert Frisch

Tenko Yamashita

Veeraraghavan S Basker

Harm Peter Hofstee

Jente Benedict Kuang

Hung Cai Ngo

Martin Eckert

Siegfried K Wiedmann

Leon Jacob Sigal

Tobias Gemmeke

Friedrich C Wernicke

Antje Mueller

Stephen Douglas Posluszny

Tak H Ning

Manoj N Kumar

K Paul Muller

Philip Joseph Oldiges

Ethan Harrison Cannon

Michael Kevin Ciraula

Jeffrey Paul Soreff

Aj KleinOsowski

Erwin Behnen

Stefan Buettner

Guenter Mayer

Jurgen Pille

Roland Metzger

David William Boerstler

Manfred Schmidt

William Vincent Huott

Anthony Gus Aipperspach

Hans-Werner Tast

Juergen Koehl

Petra Leber

Erich Klink

Wilhelm Ernst Haller

Gottfried Andreas Goldrian

Asmus Hetzel

Roland Frech

Parsotam Trikam Patel

Holger Wetter

Sebastian Ehrenreich

Ulrich Krauch

Friedrich Schroeder

Alexander Albert Woerner

Klaus Helwig

Udo Wille

Wolfram M Sauer

Stefan Bonsels

Peter Hofstee

Joseph M Poplawski, Jr

Werner Soell

Stefan Buttner

Jorg Wedeck

Horst Fuhrmann

Kurt Ganssloser

An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.

Integrated circuit with vertical structures on nodes of a grid

An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.

Microelectronic device with a memory element utilizing stacked vertical devices

An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.

Buried conductive layer supplying digital circuits

An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.

Microelectronic device utilizing stacked vertical devices

A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.

Current-mode sense amplifier

A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Structure for reducing pre-charge voltage for static random-access memory arrays

A method includes selectively degrading a current capacity of a first finned-field-effect-transistor (finFET) relative to a second finFET by forming a material on a fin of the first finFET to increase a current resistance of the first finFET. The second finFET is electrically connected to the first finFET in a circuit such that a current flow through the second finFET is a multiple of a current flow through the first finFET.

Selectively degrading current resistance of field effect transistor devices

A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.

A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.

An optical through silicon via is formed in a silicon substrate of an integrated circuit. A photo detector is formed within the integrated circuit and is optically coupled to a first side of the optical through silicon via. A light generating source optically coupled to a second side of the optical through silicon via is provided. The photo detector is configured to receive a light, generated by the light generating source, propagating through the optical through silicon via. The light, generated by the light generating source, is controlled by a signal generated by a signal generating source.

Signal distribution in integrated circuit using optical through silicon via

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Sindelfingen, Germany

Dieter F Wendel