Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Didier Salle

Birama Goumballa

Cristian Pavao Moreira

Olivier Vincent Doare

Cristian Pavao-Moreira

Jean-Stephane Vigier

Pierre Pascal Savary

Julien Orlando

Olivier Vincent Doaré

Hugues Beaulaton

Gilles Montoriol

Andres Barrilado Gonzalez

Dominique Delbecq

Thierry Cassagnes

Christophe Landez

Stephane Damien Thuries

Gerald Haennig

Ira G Miller

Vincent Pierre Martinez

Hao Li

Robert Gach

Stephane Damien Thuriés

Akbar Ghazinour

Stephane Dugalleix

Stephane Colomines

Harish Nandagopal

Jean-Stéphane Vigier

Stéphane Colomines

Arnaud Girardot

Sylvain Roudiere

Olivier Doaré

Gérald Haennig

Andres Barrilado-Gonzales

An integrated circuit device includes an integrated circuit device die and a substrate. The integrated circuit device die includes a plurality of first contact pads. The first contact pads include a pair of first signal contact pads configured to provide a differential signal port of the integrated circuit device die. The differential signal port is configured to operate at a predetermined frequency. The substrate includes a plurality of second contact pads on a first surface of the substrate. The second contact pads are configured to be soldered to a printed circuit board, and include a pair of second signal contact pads. The integrated circuit device die is affixed to a second surface of the substrate via the first contact pads. The substrate includes a pair of circuit paths that each couple one of the first signal contact pads to an associated one of the second signal contact pads. The pair of circuit paths each have a length to provide a half-wave matching network at the predetermined frequency to match a single-ended signal at the pair of second signal pads to the differential signal port.

Integrated millimeter-wave dual-mode matching network

A mechanism is provided to reduce interference between vehicular radar systems through communicating radar parameters and physical orientation between vehicles and then using directional information to form clusters of radars, which will have consistent modulation parameters. Radar modulation parameters, such as starting frequency, center frequency, bandwidth, slope, ramp direction, timing, and the like for frequency-modulated continuous-wave (FMCW) radars, are adjusted to reduce or eliminate inter-cluster direct interference between clusters oriented in different directions. For other types of radars, in some embodiments, other operational parameters can be adjusted. In some embodiments, some modulation parameters also can be adjusted to reduce or eliminate intra-cluster indirect interference.

System and method for radar interference mitigation using clustering

A communication unit includes a plurality of cascaded devices that include at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device and at least one slave device each include: a demodulator circuit configured to receive a distributed reference clock signal and re-create a system clock signal therefrom; a clock generation circuit that includes an internally-generated reference phase locked loop configured to receive the re-created system clock signal to create a master-slave clock signal; and an analog-to-digital converter, ADC, coupled to the reference phase locked loop and configured to use a same master-slave clock signal to align respective sampling instants between each ADC of the at least one master device and at least one slave device.

Communication unit, integrated circuits and method for clock and data synchronization

A transceiver includes a transmitter, a frequency synthesizer coupled to the transmitter, a receiver coupled to the frequency synthesizer and a voltage sensor; and a digital controller coupled to the voltage sensor, the receiver, and the transmitter, wherein based on a DC voltage measurement of an IF signal made by the voltage sensor, a relative phase adjustment occurs of a relative phase associated with a local oscillator (LO) port and a radio frequency (RF) port of the receiver.

Leakage cancellation in a radar receiver

A communication unit () is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit () configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (); and transmit the modulated master-slave clock signal () to the at least one slave device. The at least one slave device comprises a demodulator circuit () configured to: receive and demodulate the modulated master-slave clock signal (); and re-create therefrom the system clock signal () and the frame start signal ().

Communication unit and method for clock distribution and synchronization

A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.

Boosted return time for fast chirp PLL and calibration method

A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

Phase preset for fast chirp PLL

A communication unit () is described that includes a plurality of cascaded devices that comprise at least one master device () and at least one slave device () configured in a master-slave arrangement. The at least one master device () and at least one slave device () each comprise: an analog-to-digital converter, ADC, () configured to use a same re-created system clock signal () to align respective sampling instants between each ADC (). The at least one master device () comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (), configured to output a system clock signal (); and a modulator circuit () coupled to the clock generation circuit and configured to receive and distribute the system clock signal (). The at least one master device () and at least one slave device () each comprise: a demodulator circuit () configured to receive the distributed system clock signal () and re-create therefrom a synchronized system clock signal () used by a respective ADC, () of each of the the master device () and at least one slave device ().

A method for synchronizing a cascaded RADAR system () includes modulating () with a master RADAR system (), an amplitude of a sequence of clock cycles of a clock () in response to a Ramp Frame Start (RFS) signal (). The master RADAR system determines () a duration () of the sequence of clock cycles based on a code. A slave RADAR system () demodulates () the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes () the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.

Time-encoded messaging for radar cascaded synchronization system

An example apparatus () is for use for use with front-end circuitry () to transmit and receive radar wave signals, The apparatus () includes digital phase locked loop (PLL) circuitry () and a control circuit (). The digital PLL circuitry () provides a chirp sequence with frequency modulated continuous wave signals (FMCW), the FMCW signals being chirps containing a start frequency and a stop frequency, representing a selected chirp bandwidth (BW). The digital PLL circuitry () includes the DCO circuit () which frequency resolution is configured and arranged to be tuned relative to the selected chirp BW, the frequency resolution configured in response to a selected level of capacitance. The control circuit () controls the selected level of capacitance used by the DCO circuit () by changing the frequency resolution of the DCO according to the selected chirp BW, wherein different frequency resolutions are used for a first selected chirp BW and for a second selected chirp BW.

Methods and apparatuses for digitally controlled oscillator frequency resolution control

Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.

Temperature sensor and calibration method thereof having high accuracy

A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.

System and method for calibrating a time to digital converter device

A digital synthesizer includes a ramp generator that generates a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, that receives the FCW signal and outputs a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator that compares a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit.

Digital synthesizer, communication unit and method therefor

A device comprising: a voltage reference supply, configured to provide a reference voltage that varies in response to temperature according to a predefined relationship; a temperature sensor providing a temperature signal indicating a temperature; a first controller configured to receive the temperature signal and to output a control signal; an LC-DCO receiving the reference voltage and providing an output signal with a frequency from an LC circuit, the LC-DCO comprising a switched capacitor bank configured to provide temperature compensation by varying an effective capacitance in the LC circuit in response to the control signal.

Digitally controlled oscillator with temperature compensation

A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO configured to receive the FCW signal; a feedback loop; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply at least one gain from a plurality of selectable gains to the N-bit oscillator control signal that set a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth; and calculate and apply a gain offset dependent upon the selected gain that is adapted when the selected gain is changed.

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Toulouse, France

Didier Salle