Alcatel N.v.

International Standard Electric Corporation

Didier Rene Haspeslagh

Dirk H Rabaey

Filip Marcel Louagie

Zhong Yuan Chang

Erik Moerman

Cornelius Rabaey

To go from a coupled high level to a decoupled low level, a source unit (SU) of a transmitter (T) must be decoupled from a transmission line (TL) by a impedance unit (IU). As a result, oscillatory transition phenomena appear in the output signal and this signal possibly goes beyond a prescribed template. To avoid such overshoot problems the present transmitter (T) decreases the signal level during a decrease period before decoupling the source unit (SU) from the transmission line (TL). Therefore a source control circuit (SCC) is included in the control unit (CU) of the transmitter (T) for controlling the source level in such a way that the output signal level is decreasing.

Transmission method and transmitter for signals with a decoupled low

A time-continuous tunable Gm-C integrator including a 'super Gm' differential input stage (O1; MI1/O2, MI2) and using linear and constant degeneration resistors (R1/R2) for obtaining the most optimal linear input-voltage to output-current conversion is tunable in a time-continuous manner. The integrator is provided with three tuning CMOS transistors (MU1, MU2, MU3) controlling the integrating currents flowing between the input stages and from the input stages towards the outputs (OP/ON). By a suitable control of the tuning transistors and owing to the fact that the voltage swing across the latter is small, it is possible to obtain a perfectly linear transconductance (Gm) characteristic over the whole operating range of the integrator.

Linear tunable Gm-C integrator

In a digital sigma-delta modulator with multi-phase operations by time-sharing including an adder to produce multiple integration, an arrangement includes switching circuitry for alternately establishing one of: a connection between a first input of the adder and an input of the modulator; and connections between the adder output and the first input of the adder by way of a first integration delay circuit, and the adder output and a second input of the adder by way of a second delay circuit.

Digital sigma-delta modulator and arithmetic overflow protected adder

A device (MAM) including a common data resource (RAM) to which a first (PR) and several second (LC) stations are coupled. This device includes a first transmission circuit (DB, MD, LD2, LD1, DBU) coupling the common resource and the first station and, for each of the second stations, a second transmission circuit (DB, MD) coupling the common resource and a buffer circuit (LR; LW) and a third transmission circuit (PISO, SO; SI, SIPO) coupling the buffer circuit and the corresponding second station and which is used at predetermined moments (T1, T2, T3; T4). The device also includes a priority circuit (CLC, SG) which grants the highest priority to the requests for the use of the first transmission circuit and the following priorities to the requests for the use of the second transmission circuits in decreasing order of the frequencies (SOS; SIS) of the corresponding predetermined moments.

Multi-access device

A signal generator for generating a pulse wavetrain signal with each pulse having slopes at both the leading and trailing edges and the generated signal having a predetermined amplitude between pulses, the signal generator including: circuit components for generating first and second pulse signals which vary between first and second reference levels, with the second signal being inverted with respect to the first signal and each signal having corresponding sloping leading and trailing edges, circuit components for comparing the first and second pulse signals to derive a first control signal indicative of the presence of a pulse and a second control signal indicative of the period between pulses, and a switching device connected to receive a signal containing the first and second pulse signals and controlled by the first and second control signals to provide at an output a pulse during the first control signal and a predetermined reference level during the second control signal, whereby the predetermined reference level between pulses is always known.

Electronic circuits and signal generator using them

Pulse Code Modulation (PCM) translator for translating a PCM input word into a PCM output word, one of said words being in accordance with a compressed code and the other with a linear code, characterized in that it is adapted to convert the binary bits of the input word into those of the output word in accordance with either the A-law or the mu-law. The circuit forms part of a telephone line circuit (LC) connected between a telephone line (LI) and a digital switching network (SNW) and comprising the cascade connection of a subscriber line interface (SLIC) able to perform line control and supervision, a digital signal processor (DSP) mainly adapted to execute analog-to-digital and digital-to-analog conversion operations, the above transcoder circuit and a dual processor terminal controller (DPTC) which deals with the general control of the line circuit. The DSP only processes linear PCM signals, whereas the DPTC solely operates on companded PCM signals.

Growing community of inventors

Harelbeke, Belgium

Didier Rene Haspeslagh