International Business Machines Corporation

Didier R Louis

Andre R Steimle

Pascal R Tannhof

John Steven Dodson

Jeffrey A Stuecheli

Eric Eugene Retter

Bernard Desrosiers

Guy Paillet

Ghislain Imbert De Tremiolles

Catherine Godefroy

Didier Pinchon

Jean-Yves Boulet

Andr&eacute; Steimle

A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Dynamically adjusting read data return sizes based on interconnect bus utilization

In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>&equals;K&times;n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a &ldquo;thermometric&rdquo; coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.

Method and circuits for performing the quick search of the minimum/maximum value among a set of numbers

A diagnostic method engages all the neurons of an artificial neural network (ANN) based on mapping an input space defined by vector components based on category, context, and actual field of influence (AIF). The method includes the steps loading the components of a first and second input vectors into the ANN; engaging all the neurons of a same prototype; having all the neurons compute their own distance between the respective prototypes and the second input vector (which should be the same if the neurons were good); determining the minimum distance Dmin and comparing Dmin with a distance D measured between the first and the second input vectors. If Dmin<D, it is indicative that at least one failing neuron exists (i.e., either the distance, the category or the AIF value differs from a predetermined expected value), in which case the failing neuron is isolated. If Dmin&gE;D, the good neurons of the ANN are deselected, preventing the good neurons from further learning/recognition processing; and repeating the previous steps until the ANN is empty. The present method provides a fast and inexpensive integrity diagnostic of the neurons forming an ANN at the cost of only a few logic gates.

Method and circuit for performing the integrity diagnostic of an artificial neural network

The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the feed back and control signals. The R/W memory block, typically a RAM, is common to all neurons to avoid circuit duplication, increasing thereby the number of neurons integrated in the chip. The R/W memory stores the prototype components. Each neuron comprises a computation block, a register block, an evaluation block and a daisy chain block to chain the neurons. All these blocks (except the computation block) have a symmetric structure and are designed so that each neuron may operate in a dual manner, i.e. either as a single neuron (single mode) or as two independent neurons (dual mode). Each neuron generates local signals. The neural chip further includes an OR circuit which performs an OR function for all corresponding local signals to generate global signals that are merged in an on-chip common communication bus shared by all neurons of the chip. The R/W memory block, the neurons and the OR circuit form an artificial neural network having high flexibility due to this dual mode feature which allows to mix single and dual neurons in the ANN.

Neural chip architecture and neural networks incorporated therein

The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block substantially have a symmetric construction. Registers are used to store data: the local norm and context, the distance, the AIF value and the category. The improved neuron further needs some R/W memory capacity which may be placed either in the neuron or outside. The evaluation circuit is connected to an output bus to generate global signals thereon. The daisy chain block allows to chain the improved neuron with others to form an artificial neural network (ANN). The improved neuron may work either as a single neuron (single mode) or as two independent neurons (dual mode). In the latter case, the computation block, which is common to the two dual neurons, must operate sequentially to service one neuron after the other. The selection between the two modes (single/dual) is made by the user which stores a specific logic value in a dedicated register of the control logic circuitry in each improved neuron.

Neuron architecture having a dual structure and neural networks incorporating the same

In each neuron in a neural network of a plurality of neuron circuits either in an engaged or a free state, a pre-charge circuit, that allows loading the components of an input vector (A) only into a determined free neuron circuit during a recognition phase as a potential prototype vector (B) attached to the determined neuron circuit. The pre-charge circuit is a weight memory (251) controlled by a memory control signal (RS) and the circuit generating the memory control signal. The memory control signal identifies the determined free neuron circuit. During the recognition phase, the memory control signal is active only for the determined free neuron circuit. When the neural network is a chain of neuron circuits, the determined free neuron circuit is the first free neuron in the chain. The input vector components on an input data bus (DATA-BUS) are connected to the weight memory of all neuron circuits. The data therefrom are available in each neuron on an output data bus (RAM-BUS). The pre-charge circuit may further include an address counter (252) for addressing the weight memory and a register (253) to latch the data output on the output data bus. After the determined neuron circuit has been engaged, the contents of its weight memory cannot be modified. Pre-charging the input vector during the recognition phase makes the engagement process more efficient and significantly reduces learning time in learning the input vector.

Circuit for pre-charging a free neuron circuit

In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector. A minimum distance determination circuit determines the minimum distance Dmin among all the calculated distances from all of the neuron circuits of the neural network and generates a local output signal of the distance type. The circuit may be used to search and sort categories. The feed-back signal is collectively generated by all the neuron circuits by ORing all the local distances/categories. A daisy chain circuit is serially connected to corresponding daisy chain circuits of two adjacent neuron circuits to chain the neurons together. The daisy chain circuit also determines the neuron circuit state as free or engaged. Finally, a context circuitry enables or inhibits neuron participation with other neuron circuits in generation of the feedback signal.

Neuron circuit

An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.&lt;1), determining the value of xi and computing (x-xi) according to the IEEE 754 standard floating-point format having a first circuit arrangement operative to perform pipeline operations on a N bit mantissa; the output of the first circuit arrangement being connected to a normalizer circuit of N+4 bits whose three left-most inputs are tied to 'zero' and whose three left-most out bits J(0:2) are output on a three-bits bus (J-BUS). Also incorporated is a leading zero detector/encoder circuit and a second circuit arrangement operative to perform pipeline operations on exponents connected to an encoder circuit whose output controls the aligner circuit and a selector circuit driven by the outputs of the detector/encoder circuit and encoder circuit whose output controls the normalizer circuit; a xi determining circuit that generates the xi mantissa on a xi-BUS connected to the first circuit arrangement such that: mantissa xi=0=K(1) K(2) 1 0 . . . , 0, and a read-only memory to store the F(xi) values whose output is connected to inputs of the first and second circuits for the respective mantissa and exponent parts of F(xi).

Apparatus for argument reduction in exponential computations of IEEE

A numeric data coprocessor having an execution unit adapted to efficiently execute addition/subtraction operations on floating-point numbers in compliance with the IEEE standard 754. The mantissa adder carry out bit resulting from the operation on two operands X and Y is directly concatenated with the mantissa adder result in the mantissa output register to be the MSB thereof. Simultaneously, a 1 is added to the exponent of operand X or Y with the highest value. The final result is found after normalizing, regardless of whether the carry out bit is 1 or 0. In its hardware embodiment, taking for example the 80-bit double extended precision IEEE format, the mantissa output register has 68 positions. The 68th supplementary position is fed by the carry out bit generated by the mantissa adder at the 'carry out' output. The 'Force Carry' input of the exponent adder is activated by the control logic circuitry to add a 1 to the operand exponent with the highest value.

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Fontainebleau, France

Didier R Louis