International Business Machines Corporation

Didier Malcavet

Andre R Steimle

Gerard Boudon

David Pereira

Vincent Vallet

A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Self-synchronizing bit error analyzer and circuit

A data recovery circuit employing an oversampling technique. The incoming serial data stream with jitter is oversampled by means of the multiple phases of a reference clock to produce data samples. Each sample is compared to the samples collected with the next clock phase in an edge detector circuit to determine the presence of a data edge. The edge information, representative of the data edge positions, is stored and accumulated in the form of a bit map. A detection/suppression circuit detects and suppresses edges which are not adjacent to any other edge in the edge memory. A selection determination circuit uses the edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Data recovery circuits using oversampling for maverick edge detection/suppression

A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator

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Champdeuil, France

Didier Malcavet