Commissariat a L'energie Atomique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Xantima LLC

Other

Commissariat a L'engerie Atomique

Didier Lattard

Bernard Piaget

Didier Varreau

Laurent Ouvry

Norbert Daniele

Marc Laugeois

Christophe Boulanger

Jean-Ren&eacute; Lequepeys

Jean-René Lequepeys

Fabien Clermidy

Mathieu Bouvier Des Noes

Dominique Noguet

Pascal Vivet

Christian Bernard

Sébastien Thuries

Perrine Batude

Olivier Billoint

Sébastien Leveque

Gilles Sicard

Romain Lemaire

Warody Lombardi

Jean-Remy Savel

Jene-Remi Savel

Jean Rene Lequepeys

S&eacute;bastien Leveque

Bouvier Des Noes Mathieu

Jean-Remi Savel

Hughes Metras

Walid Lafi

Vincent Lenoir

Three-dimensional microelectronic circuit with optimised distribution of its digital and analogue functions

A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Conception of a 3D circuit comprising macros

A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.

Integrated circuit comprising macros and method of fabricating the same

A 3D stack includes a first chip having first interconnection pads of rectangular section, the first interconnection pads having a first pitch in a first direction and a second pitch in a second direction perpendicular to the first direction; and a second chip having second interconnection pads, the second interconnection pads having a third pitch in the first direction and a fourth pitch in the second direction, at least one part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second chips. The first interconnection pads have a first dimension in the first direction equal to m times the third pitch and a second dimension in the second direction equal to n times the fourth pitch. The first interconnection pads are separated two by two in the first direction by a first distance equal to q times the third pitch.

3D stack of electronic chips

An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network.

Face-to-face three-dimensional integrated circuit of simplified structure

A method for decoding a data symbol carried by a signal received by a receiver of a communication system, the data symbol being modulated by a spread code sequence selected from a plurality of spread code sequences being quasi-orthogonal to each other to differentiate the symbol from other data symbols, and being received as a set of modulation bits, the method including a step of correlating the modulated data symbol received with each of the plurality of spread code sequences, and the correlating step is preceded by a step of sub-sampling the modulated data symbol received to mask one or more of the modulation bits therein, such that the step of correlating the sub-sampled data symbol received is carried out only for the non-masked modulation bits. It extends to a demodulation unit configured for the implementation of this method, and to a receiver integrating such a unit.

Method for self-adaptively demodulating quasi-orthogonal signals, demodulation unit and radio signal receiver

This electronic chip includes functional modules each including a single processing unit and a single routing unit (E) connected to one another, and connections, called routing connections, each of which has at least one end connected to the routing unit of a functional module, where the routing connections connect between themselves the routing units of the functional modules so as to allow routing of data between the processing units of the functional modules. The routing unit (E) of at least one functional module, called a split routing unit, includes two routers (E,E), called respectively a first-level router and a second-level router, which are connected to one another, where the first-level router is moreover connected to at least two routing connections, and where the second-level router is moreover connected to the processing unit of this functional module and connected to at least one other routing connection.

Electronic chip and integrated circuit including a split routing unit having first-level routers for intra-layer transmissions and second-level routers for inter-layer transmissions and transmissions to the processing units

This invention relates to a system on chip for data flow type application. The system comprises a network on chip, a central controller and processing units connected to said network via associated network interfaces. A processing unit and/or its associated network interface can be configured on command from the central controller or on a command incorporated in a data packet to be processed. The network interface comprises a client module that can request a configuration server to transmit the parameters of a configuration that is unavailable in the interface. The invention also relates to a mobile terminal/ a base station comprising a base band modem implemented by such a system on chip.

System on chip with interface and processing unit configurations provided by a configuration server

A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation management signals (HS, SS, ID) are formed and, under the control of these signals, a header is inserted before a data group and after it a correcting code. At receive end, these synchronisation management signals are reconstituted, the presence of a header is detected and any erroneous symbols are corrected. The invention also provides for an auto-synchronised coder and a decoder and for a transmitter and a receiver using them.

Data transmission process with auto-synchronized correcting code, auto-synchronized coder and decoder, corresponding to transmitter and receiver

Receiver module and receiver formed from several cascaded module. The module comprises inputs (E, E, E, E) and outputs (S, S, S, S) connected toaselectionmeans (44)circuit,toaswitchingmeans (45)circuit,and toadecodingmeans (46, 58, 60)circuit. Such modules can be cascaded by simply connecting the corresponding inputs and outputs.The final module delivers the transmitted information.Application to differential phase modulation and orthogonal modulation spread spectrum digital transmission.

Receiver module and receiver formed from several cascaded modules

Data transmission process with auto-synchronized correcting code, auto-synchronized coder and decoder, corresponding transmitter and receiver

A receiver is configured to receive signals corresponding to spread spectrum information symbol streams. The receiver includes a plurality of channel circuits for receiving signals. Each channel circuit is responsive to a received signal for recovering an associated information signal therefrom. The associated information signal is spread by a sequence associated with the respective channel circuit. Each channel circuit is controlled by a clock signal derived by at least a first channel circuit of the plurality of channel circuits. The at least first channel circuit is responsive to the received signal for generating the clock signal by digitally filtering the received signal using digital filter coefficients adapted to the sequence associated with the at least first channel circuit.

Receiver for a CDMA system

A data processing method in a network on chip formed of a plurality of processors configured to communicate between one another, and at least one network controller configured to initialize communications in the network, the method including: receiving and storing in a memory by a first processor, one or more credit management configuration programs received from the network controller, and establishing a first communication between at least said first processor and at least one second processor.

NoC semi-automatic communication architecture for 'data flows' applications

The invention relates to a device for exchanging digital data between several sources and at least one hub in a CDMA system, characterised in that it comprises a number n of digital transmission/reception circuits () installed in parallel, each circuit () comprising a transmitter () comprising means of generating an integer number Nof codes that will be used for spectral spreading of data to be transmitted and a receiver () comprising means () of detecting the access of new sources to the CDMA system transmission channel and means () of generating synchronisation signals and power control signals corresponding to each detected new source.

Digital data exchange device in a CDMA system

A receiver for transmission and parallel interference has multiple access interference suppression stages having K channels, each comprising a correlation device corresponding to a particular pseudorandom sequence and interference generation and suppression device. Each stage delivers to the following stage signals at least partly freed from multiple access interferences. A decision stage receives the signals from the channels of the preceding suppression stage. Each decision stage has a correlation device corresponding to one of the pseudorandom sequences and decision device to deliver data. Devices for producing synchronization signals can control the interference suppression and the decision device. The devices producing the synchronization signals have components placed in the channels of the final stage. Further, the synchronization signals produced by these devices control the decision device of the channels of the final stage and the interference estimation device of the at least one interference suppression stages following appropriate time shifts.

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Rencurel, France

Didier Lattard