Synopsys, Inc.

Dick Liu

Zuo Dai

Ming Su

Randy Bishop

Jon Francis Bendicksen

John Hapli

Jingyu Xu

Scott I Chase

Jun Wang

Jun Lu

Hu Cai

Xiaoxu Cheng

Hau-Yung Chen

Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.

In-design real-time electrical impact verification flow

Systems and techniques are described for determining a resistance of a conducting structure. The conducting structure can be partitioned into a set of polygons based on (1) equipotential lines and (2) boundaries of the conducting structure. Next, a matrix equation can be constructed, wherein for at least one polygon in the set of polygons, electric potentials of boundary elements on the boundaries of the polygon are represented by linear combinations of electric potentials of two or more equipotential lines. The resistance of the conducting structure can then be determined by solving the matrix equation.

Determining the resistance of a conducting structure

Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

High performance design rule checking technique

Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.

Low-overhead multi-patterning design rule check

Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.

Real time DRC assistance for manual layout editing

Roughly described, a design rule data set includes rules on derived layers. The rules are checked by traversing the corners of physical shapes, and for each corner, populating a layout topology database with values gleaned from that corner location, including values involving derived layers. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations, including violations of design rules defined on derived layers. Violations are reported in real time during manual editing of the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, scanning in the direction of the edge orientations. Scans stop only at corner positions on physical layers, and populate the layout topology database with what information can be gleaned based on the current scan line, including information about derived layers. The scans need not reach corners simultaneously.

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Saratoga, CA, United States of America

Dick Liu