Lsi Logic Corporation

Quickturn Design Systems, Inc.

Dick L Liu

Robert M Walker, Iii

Thomas B Huang

Jeong-Tyng Li

Kenneth S Choi

An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting 'read-back' trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

Method and apparatus for debugging reconfigurable emulation systems

A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

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Saratoga, CA, United States of America

Dick L Liu