Xilinx, Inc.

Diarmuid Collins

Ionut C Cical

Edward Cullen

John K Jennings

Umanath R Kamath

Christophe Erdmann

Bruno Miguel Vaz

Examples described herein provide an apparatus having a circuit with a grounding circuit and a switch. The apparatus generally includes a gate induced drain leakage (GIDL) protection circuit coupled to the switch and to an output voltage. The GIDL protection circuit may include a switch protection circuit configured to maintain a drain voltage of the switch less than a first supply voltage (V) when the circuit is in an OFF state; and a ground protection circuit configured to maintain a drain voltage of the grounding circuit less than the first supply voltage when the circuit is in an ON state.

Gate induced drain leakage robust bootstrapped switch

A temperature sensor includes a current source to produce a first bias current and a second bias current, a plurality of diodes, and temperature estimation circuitry. The plurality of diodes includes at least a first diode to receive the first bias current and a second diode to receive the second bias current. The temperature estimate circuitry measures a first voltage bias across the first diode resulting from the first bias current and a second voltage bias across the second diode resulting from the second bias current, and estimates a temperature of an environment of the temperature sensor based at least in part on the first voltage bias and the second voltage bias. The temperature sensor further includes error detection circuitry to measure at least one of the first or second bias currents and determine an amount of error in the temperature estimate based at least in part on the measurement.

Bias current variation correction for complementary metal-oxide-semiconductor (CMOS) temperature sensor

A control circuit used in an integrated circuit device is described. The control circuit comprises a startup timer configured to generate a startup timing signal; a startup circuit configured to generate a startup control signal; and a switching element coupled between the startup circuit and a load; wherein the switching element applies the startup control signal to the load during a startup period associated with the startup timing signal. A method of controlling an operation of an integrated circuit device is also described.

Control circuit for and method of controlling an operation of an integrated circuit device

A complementary metal-oxide-semiconductor (CMOS) switching system with increased supply rejection is disclosed. The system comprises a voltage regulator and a CMOS circuit. The voltage regulator receives a supply voltage and generates a regulated voltage by regulating an amplitude of the received supply voltage. The CMOS circuit includes an input terminal to receive a first voltage, switching circuitry to selectively couple the CMOS circuit to the voltage regulator in one of a plurality of configurations, and an output terminal to output a second voltage based at least in part on the first voltage and the regulated voltage when the CMOS circuit is coupled to the voltage regulator in a first configuration of the plurality of configurations.

Method of increased supply rejection on single-ended complementary metal-oxide-semiconductor (CMOS) switches

A voltage divider is described. The voltage divider comprises a pair of input nodes for receiving an input signal; a pair of output nodes configured to generate an output signal; a first capacitor having a first terminal coupled to a first output node of the pair of output nodes and a second terminal coupled to a second output node of the pair of output nodes; and a second capacitor having first terminal and a second terminal; a bypass switch having a first terminal coupled to the first terminal of the second capacitor and a second terminal coupled to the second terminal of the second capacitor; and a charge sharing switch coupled to the second terminal of the second capacitor; wherein the bypass switch and the charge sharing switch enable the sharing of charge between the first capacitor and the second capacitor.

Voltage divider and method of implementing a voltage divider

A device may include a voltage-to-current converter circuit having an operational transconductance amplifier (OTA), the voltage-to-current converter circuit for generating a bias current that is proportional to a reference voltage at a reference voltage input port of the OTA, and a bias current feedback path for providing the bias current to a bias current input port of the OTA. The device may further include a startup current generator circuit coupled to the bias current input port of the OTA, the startup current generator circuit controllable to provide a startup current to the bias current input port during a startup of the device and to be deactivated after the startup of the device.

Self-biased operational transconductance amplifier-based reference circuit

An example capacitive digital-to-analog converter (CDAC) includes: a first plurality of capacitors consisting of M&#x2212;1 capacitors, where M is an integer greater than one, the first plurality of capacitors including top plates coupled to a first node; a second plurality of capacitors consisting of M&#x2212;1 capacitors, the second plurality of capacitors including top plates coupled to a second node; a first plurality of switches consisting of M&#x2212;1 switches coupled to bottom plates of the respective M&#x2212;1 capacitors of the first plurality of capacitors, the first plurality of switches further coupled to a third node providing a supply voltage and a fourth node providing a ground voltage; a second plurality of switches consisting of M&#x2212;1 switches coupled to bottom plates of the respective M&#x2212;1 capacitors of the second plurality of capacitors, the second plurality of switches coupled to the third node and the fourth node; and a control circuit including an input consisting of M bits for receiving an M bit code and an output consisting of 2*(M&#x2212;1) bits for providing a first M&#x2212;1 bit code to respectively control the M&#x2212;1 switches of the first plurality of switches and a second M&#x2212;1 bit code to respectively control the M&#x2212;1 switches of the second plurality of switches.

Capacitive digital-to-analog converter

A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

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Dunshaughlin, Ireland

Diarmuid Collins