Lontium Semiconductor Corporation

Diansheng Ren

Jin Su

Feng Chen

Shenghui Bao

Lianliang Tai

Hongfeng Xia

Hui Bian

Fengyu Gao

Lei Li

Cheng Tao

Xi Xu

Guangren Li

Dafeng Zhou

Dawei Wu

Dexing Luo

Xianghao Guo

Changqian Xie

Chuanxing Liu

Haowei Guan

A multimedia data transmission apparatus and method are provided. In the method, a data receiver receives at least one channel of multimedia data and transmits the received multimedia data to a selector and a data synthesis module. The selector selects target multimedia data from the received multimedia data and transmits the target multimedia data to a data processing module. The data processing module performs a format conversion on the target multimedia data to obtain converted data and transmits the converted data to a data transmitting module. The data synthesis module synthesizes the received multimedia data to obtain synthesized data and transmits the synthesized data to the data transmitting module. The data transmitting module transmits the converted data to a first processing device and transmits the synthesized data to a second processing device.

Multimedia data transmission apparatus and method

A deserializer is provided. The deserializer includes a data receiver, an RCC transmitter, an I2C master, a command determination device, a video transmitter, a video processing device and an I2S transmitter. The data receiver analyzes raw data sent to the deserializer to obtain audio data, video data and/or command data. The I2S transmitter sends the audio data to the outside of the deserializer. The video processing equipment performs a format conversion on the video data and sends the video data to the outside of the deserializer. The command determination device determines the command data, and sends the command data to the outside of the deserializer in response to a determination result indicating that the command data is a deserializer external command.

Deserializer

A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Storage device and method for manufacturing the same

A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.

Clock and data recovery circuit and phase interpolator therefor

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Anhui, China

Diansheng Ren