Wuhan Tianma Micro-Electronics Co., Ltd

Wuhan China Star Optoelectronics Technology Co., Ltd.

Dian Zhang

Ronglei Dai

Zuomin Liao

Wenshuai Zhang

A display panel includes a display region, a shift register region, and a compensation region. The display region includes multiple display pixel groups. A display pixel group includes multiple first pixel units arranged in sequence along a first direction. The shift register region includes first shift register units and second shift register units. A first shift register unit is electrically connected to m display pixel groups, and a second shift register unit is electrically connected to n display pixel groups, where m and n are positive integers, and m>n. The compensation region includes load compensation units electrically connected to the second shift register units.

Display panel and display device

A display panel and a display device are provided. A first display area of the display panel is located at two sides of a second display area, and a first data line in the first display area is electrically connected to a demultiplexing unit through a first connection line segment and a second connection line segment. The second connection line segment is located between the adjacent first sub-data line and second sub-data line in the second display area, and a distance between the second connection line segment and the first sub-data line is smaller than a distance between the second connection line segment and the second sub-data line. The control terminal of the switch element in the demultiplexing unit corresponding to the first data line is connected to a same switch control line as the control terminal of the switch element corresponding to the first sub-data line.

A display panel includes a plurality of pixel circuits, a plurality of signal write control lines, a plurality of reset control lines, a plurality of data lines, and a plurality of connection wires; the connection wire includes a first connection wire segment and a second connection wire segment; and a reset control signal provided for the (N+i+1)-th row of pixel circuits is an (N+i+1)-th reset control signal, and a write control signal provided for the N-th row of pixel circuits is an N-th write control signal, where a first voltage edge and/or a second voltage edge of an enable level of the (N+i+1)-th reset control signal do not overlap an enable level of the N-th write control signal; and in an enable level of the same reset control signal, the second voltage edge is after the first voltage edge, N is a positive integer, and i is a natural number.

A display panel and a display device are provided. The display panel includes first data lines located in a first area and connected to first sub-pixels in the first area; second data lines located in a second area and connected to second sub-pixels in the second area; transfer lines located in a display area and connected to the first data lines; and demultiplexers including N switches. Input terminals of the N switches of a same demultiplexer are connected. A first data line is connected to a demultiplexer through a transfer line. i first data lines and j second data lines are connected to output terminals of the N switches. For the same demultiplexer, light-emitting color of first sub-pixels connected to the i first data lines is same as light-emitting color of second sub-pixels connected to the j second data lines; and N≥2, and i+j=N.

A display panel and a display device are provided. A first display area of the display panel is located at least one side of a second display area, and a first data line in the first display area is electrically connected to a demultiplexing unit through a first connection line segment and a second connection line segment. The second connection line segment is located between the adjacent first sub-data line and second sub-data line in the second display area, and a distance between the second connection line segment and the first sub-data line is smaller than a distance between the second connection line segment and the second sub-data line. The control terminal of the switch element in the demultiplexing unit corresponding to the first data line is connected to a same switch control line as the control terminal of the switch element corresponding to the first sub-data line.

A MOG circuit and a display panel are provided. The MOG circuit controls the current-stage MOG circuit through the first node signal to block the input of the MUX signal. At the same time, the MOG circuit controls the current-stage MUX circuit through the second node signal such that the voltage level of the scan signal is pulled down to the voltage level of the first low voltage level signal. In this way, all the scan signals could satisfy the turn-off stage while the MUX circuit has a lower loading capability.

MOG circuit and display panel

Provided are a display panel and a display device. The display panel includes multiple pixel units, multiple scan lines, multiple data lines, a multiplexer and h control signal lines. In a same data write stage of the display panel, during a first stage, data signals are written into the multiple data lines at an enable duration of a j-th control signal, during a second stage, a first scan enable voltage edge of an i-th scan signal is located behind a first control enable voltage edge of the j-th control signal, and the data signals on the multiple data lines are written into the multiple pixel units; and a second scan enable voltage edge of the i-th scan signal in a m-th data write stage is located before a second control enable voltage edge of an n-th control signal in a (m+1)-th data write stage.

A demultiplexer gate driver circuit and a display panel are provided. The demultiplexer gate driver circuit aims at the problem that the output amplitude of the m sub-gate drive signals divided from the gate drive signal by the demultiplexer module is low, which results in a poorer All Gate On function, when the GOA circuit of the demultiplexer module is used to achieve the All Gate On function. The full-on control module is improved by connecting the full-on control module to the m sub-gate drive signals divided from the gate drive signal. The m sub-gate drive signals are directly controlled by the full-on control module to output the high potential at the same time, and there is only one threshold voltage consumption from the full-on control signal to the sub-gate drive signals. The effect of the All Gate On function is effectively improved.

Demultiplexer gate driver circuit and display panel

The present invention provides a pixel driving circuit, a display panel, and a display device. The pixel driving circuit includes: an upper plate of a liquid crystal capacitor and an upper plate of a storage capacitor both connected to a drain of a driving thin film transistor, and a lower plate of the liquid crystal capacitor and a lower plate of the storage capacitor both connected to a voltage regulator module. When the display panel is powered off, the voltage regulator module keeps a voltage difference between the upper and lower plates of the liquid crystal capacitor and the upper and lower plates of the storage capacitor constant.

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Wuhan, China

Dian Zhang