Taiwan Semiconductor Manufacturing Comp. Ltd.

Dian-Hau Chen

Hsiang-Ku Shen

Yen-Ming Chen

Chih-Fan Huang

Yuan-Yang Hsiao

Hui-Chi Chen

Tsung-Chieh Hsiao

Chen-Chiu Huang

Liang-Wei Wang

Jye-Yen Cheng

Yu-Bey Wu

Hung-Chao Kao

Sheng-Hsuan Wei

Jiing-Feng Yang

Mao-Nan Wang

Li-Yu Lee

Cheng-Lin Huang

Chii-Ping Chen

Yuh-Jier Mii

Ying-Yao Lai

Chih-Pin Chiu

Zhen-Cheng Wu

Kuo-Chin Chang

Shu-Hui Su

Tai-Yang Wu

Chih-Hsin Yang

Lee-Chung Lu

Chih-Yang Pai

Jin-Mu Yin

Yu-Jen Wang

TaiYang Wu

Wen-Chiung Tu

Tsung-Lin Lee

Yuan-Te Hou

Lin-June Wu

Shyue-Shyh Lin

Hong-Seng Shue

Ko-Bin Kao

Chun-Li Lin

Ching-Tien Ma

Chien-Huang Yeh

Ren-Guei Wu

Ru-Gun Liu

Li-Chun Tien

Feng-Cheng Yang

Wei-Yang Lee

Po-Hsiang Huang

Wen-Hao Chen

Wen-Chun Huang

Yao-Chun Chuang

Ku-Feng Lin

Yung-Chih Wang

Chung-Yi Lin

Nai-Wei Liu

Hsiang-Lin Chen

Chih-Sheng Li

Kwang-Ming Lin

Yung-Shih Cheng

Po-Sheng Lu

Ming-Hong Kao

Hsiao Ching-Wen

Pei-Ru Lee

Tzu-Hao Huang

Chih-Hao Hsieh

Juei-Kuo Wu

Ruei-Je Shiu

Hsiang-Tan Lee

Chih-Chuan Su

Chih-Ming Lai

Tien-I Bao

Zhiqiang Wu

Chung-Hsing Wang

Li-Zhen Yu

Tsai-Sheng Gau

Yi-Kan Cheng

Kuo-Nan Yang

Burn Jeng Lin

Ken-Hsien Hsieh

Chien-Hao Chen

Sung-Hui Huang

Han-Ting Tsai

Chih-Tang Peng

Jr-Hung Li

Kang-Min Kuo

Chien-Hua Huang

Kai-Wen Cheng

Chin-Shen Lin

Chi-On Chui

Chia-Cheng Ho

De-Wei Yu

Ke-Ying Su

Chih-Hung Lu

Ying-Liang Chuang

Yu-Hua Lee

Szu-Ping Tung

Shih-Wei Wang

Bo-Cyuan Lu

Yu-Ku Lin

Hsiao-Shu Chao

Ming-Hui Chih

One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.

MIM capacitor in IC heterogenous integration

A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

Selective gate air spacer formation

Disclosed semiconductor device manufacturing processes improve the flatness of a passivation layer deposited above a redistribution layer (RDL). When a thin passivation layer is deposited above the RDL, its top surface tends to become very uneven due to the large gaps that typically form over the etched portions of the RDL, particularly when the RDL is disposed over an underlying super high density metal-insulator-metal (MIM) capacitor. In order to reduce the incidence of stress concentration areas on the uneven surface, a thicker passivation layer is instead deposited to minimize gap formation therein, and a chemical mechanical planarization (CMP) process is then performed to further smooth the top surface thereof. Reduction of the stress in this manner reduces the incidence of cracking of the underlying MIM, which improves the overall pass rates of semiconductor devices so manufactured.

Semiconductor structures and methods for manufacturing the same

A method for forming a semiconductor structure includes forming a metal-insulator-metal (MIM) structure between first passivation layers over a substrate. The method also includes forming a via structure through the MIM structure and the first passivation layers. The method also includes planarizing the via structure. The method also includes forming an RDL structure over the via structure. The method also includes forming a second passivation layer over the RDL structure and the first passivation layers.

Semiconductor structure and method for forming the semiconductor structure

The present disclosure is directed to a semiconductor device. The semiconductor device includes a multi-layer interconnect structure disposed over a substrate, a dielectric layer disposed over the multi-layer interconnect structure, and a metal-insulator-metal (MIM) capacitor disposed over the dielectric layer. The MIM capacitor includes a bottom electrode disposed on a top surface of the dielectric layer, a top electrode disposed above the bottom electrode, and an insulating layer interposed between the bottom electrode and the top electrode. The bottom electrode has a slanted sidewall with respect to the top surface of the dielectric layer. The top electrode has a vertical sidewall with respect to the top surface of the dielectric layer. The insulating layer covers the slanted sidewall of the bottom electrode.

Metal-insulator-metal structure and methods of fabrication thereof

A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.

Back-end-of-line passive device structure

A semiconductor package includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first semiconductor substrate, a first bonding structure bonded to the second integrated circuit, a ferromagnetic layer surrounding the first bonding structure, and a memory cell between the first semiconductor substrate and the first bonding structure.

Semiconductor packages

A semiconductor structure and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first die having a front surface and a back surface and a second die bonded to the back surface of the first die. The first die includes a plurality of trenches adjacent the back surface and the plurality of trenches are filled with a liquid.

Semiconductor package with improved heat distribution

A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than −0.3 GPa.

Semiconductor packaging structure and method for manufacturing the same

In a method of manufacturing a semiconductor device including a magnetic random access memory (MRAM) cell, a first layer made of a conductive material is formed over a substrate. A second layer for a magnetic tunnel junction (MTJ) stack is formed over the first conductive layer. A third layer is formed over the second layer. A first hard mask pattern is formed by patterning the third layer. The MTJ stack is formed by patterning the second layer by an etching operation using the first hard mask pattern as an etching mask. The etching operation stops at the first layer. A sidewall insulating layer is formed over the MTJ stack. After the sidewall insulating layer is formed, a bottom electrode is formed by patterning the first layer to form the MRAM cell including the bottom electrode, the MTj stack and the first hard mask pattern as an upper electrode.

Magnetic random access memory and manufacturing method thereof

A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a conductive via passing through the first conductive layer and electrically connected to the first conductive layer. The chip structure includes a conductive pad over and in direct contact with the conductive via. The chip structure includes a second conductive layer over and spaced apart from the first conductive layer. The chip structure includes a first dielectric layer conformally covering a second lower portion of a sidewall of the second conductive layer. The chip structure includes a third conductive layer over the first dielectric layer.

Chip structure with conductive layer

A redistribution structure is provided. A redistribution structure according to the present disclosure includes a first dielectric layer, a mesh metal feature disposed in the first dielectric layer and including a base portion and a frame portion surrounding the base portion, a second dielectric layer disposed over the first dielectric layer and the mesh metal feature, a redistribution feature disposed over the second dielectric layer, a passivation structure disposed over the redistribution feature and the second dielectric layer, a pad opening extending through the passivation structure to expose a top surface of the redistribution feature. The redistribution feature includes a plurality of contact vias that extend through the second dielectric layer to land on the frame portion of the mesh metal feature.

Wafer test pad

A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.

Method of forming a stress reduction structure for metal-insulator-metal capacitors

A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

Structure and method for MRAM devices with a slot via

A method includes forming a magnetic tunnel junction (MTJ) stack over a substrate. The MTJ stack including a top magnetic layer, a barrier layer, and a bottom magnetic layer. The method also includes patterning the top magnetic layer in a first etch process, after the patterning of the top magnetic layer depositing a spacer on sidewalls of the patterned top magnetic layer, and patterning the bottom magnetic layer in a second etch process.

Semiconductor memory device with spacer protection and method for forming same using multi-step patterning

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Hsinchu, Taiwan

Dian-Hau Chen