Taiwan Semiconductor Manufacturing Comp. Ltd.

Dian-Hau Chen

Hsiang-Ku Shen

Yen-Ming Chen

Chih-Fan Huang

Yuan-Yang Hsiao

Hui-Chi Chen

Tsung-Chieh Hsiao

Chen-Chiu Huang

Liang-Wei Wang

Jye-Yen Cheng

Yu-Bey Wu

Hung-Chao Kao

Sheng-Hsuan Wei

Jiing-Feng Yang

Mao-Nan Wang

Cheng-Lin Huang

Chii-Ping Chen

Yuh-Jier Mii

Zhen-Cheng Wu

Kuo-Chin Chang

Shu-Hui Su

Lee-Chung Lu

Chih-Yang Pai

Jin-Mu Yin

Yuan-Te Hou

Lin-June Wu

Shyue-Shyh Lin

Hong-Seng Shue

Ko-Bin Kao

Chun-Li Lin

Ru-Gun Liu

Li-Chun Tien

Tsung-Lin Lee

Po-Hsiang Huang

Wen-Hao Chen

Wen-Chun Huang

Yao-Chun Chuang

Ku-Feng Lin

Yung-Chih Wang

Chung-Yi Lin

Nai-Wei Liu

Hsiang-Lin Chen

Chih-Sheng Li

Yung-Shih Cheng

Kwang-Ming Lin

Chih-Ming Lai

Tien-I Bao

Feng-Cheng Yang

Wei-Yang Lee

Zhiqiang Wu

Chung-Hsing Wang

Li-Zhen Yu

Tsai-Sheng Gau

Yi-Kan Cheng

Kuo-Nan Yang

Burn Jeng Lin

Ken-Hsien Hsieh

Chien-Hao Chen

Sung-Hui Huang

Chih-Tang Peng

Han-Ting Tsai

Jr-Hung Li

Kang-Min Kuo

Chien-Hua Huang

Kai-Wen Cheng

Chin-Shen Lin

Chia-Cheng Ho

Chi-On Chui

De-Wei Yu

Ke-Ying Su

Chih-Hung Lu

Ying-Liang Chuang

Yu-Hua Lee

Szu-Ping Tung

Shih-Wei Wang

Yu-Ku Lin

Bo-Cyuan Lu

Hsiao-Shu Chao

Wei-Chih Wen

Ming-Hui Chih

Chung-Min Fu

Hung-Yi Huang

Wan-Yu Lo

Min-Hsiu Hung

Cheng-Hao Hou

Yen-Chun Huang

Juing-Yi Wu

Cheng-Po Chau

Yu-Feng Yin

Ming-Shiang Lin

Li-Kong Turn

Cheng-Hung Yeh

Kuo-An Liu

Wei-Kay Chiu

Tzu-Li Lee

Tzung-Yi Tsai

Kai Tak Lam

Guan-Yao Tu

Chia-Lin Chuang

Chia-Hung Lai

The present disclosure is directed to a semiconductor device. The semiconductor device includes a multi-layer interconnect structure disposed over a substrate, a dielectric layer disposed over the multi-layer interconnect structure, and a metal-insulator-metal (MIM) capacitor disposed over the dielectric layer. The MIM capacitor includes a bottom electrode disposed on a top surface of the dielectric layer, a top electrode disposed above the bottom electrode, and an insulating layer interposed between the bottom electrode and the top electrode. The bottom electrode has a slanted sidewall with respect to the top surface of the dielectric layer. The top electrode has a vertical sidewall with respect to the top surface of the dielectric layer. The insulating layer covers the slanted sidewall of the bottom electrode.

Metal-insulator-metal structure and methods of fabrication thereof

A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.

Back-end-of-line passive device structure

A semiconductor package includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first semiconductor substrate, a first bonding structure bonded to the second integrated circuit, a ferromagnetic layer surrounding the first bonding structure, and a memory cell between the first semiconductor substrate and the first bonding structure.

Semiconductor packages

A semiconductor structure and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first die having a front surface and a back surface and a second die bonded to the back surface of the first die. The first die includes a plurality of trenches adjacent the back surface and the plurality of trenches are filled with a liquid.

Semiconductor package with improved heat distribution

A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than −0.3 GPa.

Semiconductor packaging structure and method for manufacturing the same

In a method of manufacturing a semiconductor device including a magnetic random access memory (MRAM) cell, a first layer made of a conductive material is formed over a substrate. A second layer for a magnetic tunnel junction (MTJ) stack is formed over the first conductive layer. A third layer is formed over the second layer. A first hard mask pattern is formed by patterning the third layer. The MTJ stack is formed by patterning the second layer by an etching operation using the first hard mask pattern as an etching mask. The etching operation stops at the first layer. A sidewall insulating layer is formed over the MTJ stack. After the sidewall insulating layer is formed, a bottom electrode is formed by patterning the first layer to form the MRAM cell including the bottom electrode, the MTj stack and the first hard mask pattern as an upper electrode.

Magnetic random access memory and manufacturing method thereof

A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a conductive via passing through the first conductive layer and electrically connected to the first conductive layer. The chip structure includes a conductive pad over and in direct contact with the conductive via. The chip structure includes a second conductive layer over and spaced apart from the first conductive layer. The chip structure includes a first dielectric layer conformally covering a second lower portion of a sidewall of the second conductive layer. The chip structure includes a third conductive layer over the first dielectric layer.

Chip structure with conductive layer

A redistribution structure is provided. A redistribution structure according to the present disclosure includes a first dielectric layer, a mesh metal feature disposed in the first dielectric layer and including a base portion and a frame portion surrounding the base portion, a second dielectric layer disposed over the first dielectric layer and the mesh metal feature, a redistribution feature disposed over the second dielectric layer, a passivation structure disposed over the redistribution feature and the second dielectric layer, a pad opening extending through the passivation structure to expose a top surface of the redistribution feature. The redistribution feature includes a plurality of contact vias that extend through the second dielectric layer to land on the frame portion of the mesh metal feature.

Wafer test pad

A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.

Method of forming a stress reduction structure for metal-insulator-metal capacitors

A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

Structure and method for MRAM devices with a slot via

A method includes forming a magnetic tunnel junction (MTJ) stack over a substrate. The MTJ stack including a top magnetic layer, a barrier layer, and a bottom magnetic layer. The method also includes patterning the top magnetic layer in a first etch process, after the patterning of the top magnetic layer depositing a spacer on sidewalls of the patterned top magnetic layer, and patterning the bottom magnetic layer in a second etch process.

Semiconductor memory device with spacer protection and method for forming same using multi-step patterning

Passive devices are provided. In an embodiment, a passive device includes a substrate comprising a first region and a second region, a first lower contact feature and a second lower contact feature in a dielectric layer and directly over the first region and the second region, respectively, a first vertical stack of conductive features disposed over the first region, a metal-insulator-metal (MIM) capacitor disposed over the second region and comprising a vertical stack of conductor plates, a first contact via extending through the first vertical stack of conductive features and electrically coupled to the first lower contact feature, and a second contact via extending through a portion of the vertical stack of conductor plates and electrically coupled to the second lower contact feature. A number of conductive features penetrated by the first contact via is different than a number of conductor plates penetrated by the second contact via.

Semiconductor structures and methods of forming the same

A semiconductor memory structure includes bottom electrodes formed over a substrate. The structure also includes first magnetic tunneling junction (MTJ) elements formed over the bottom electrodes in a first region and a second region of the substrate. The structure also includes second MTJ elements formed over the first MTJ elements in the first region and the second region. The structure also includes top electrodes formed over the second MTJ elements. The first MTJ elements in the first region are narrower than the second MTJ elements in the first region, and the second MTJ elements in the second region are narrower than the first MTJ elements in the second region.

Semiconductor memory structure and method for forming the semiconductor memory structure

A semiconductor device includes a substrate, a gate structure, a source region and a drain region, a conductive via and an isolation structure. The gate structure is disposed over the substrate. The source region and the drain region aside the gate structure. The conductive via is disposed in the substrate. The isolation structure is disposed in the substrate, wherein a first surface of the isolation structure is substantially flush with a first surface of the conductive via.

Semiconductor devices and method of forming the same

A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack. The MIM stack includes at least one lower conductor plate layer, a first insulator layer disposed over the at least one lower conductor plate layer, a first conductor plate layer disposed over the first insulator layer, a second insulator layer disposed over the first conductor plate layer, and a second conductor plate layer disposed over the second insulator layer. The device structure further includes a ground via extending through and electrically coupled to a first ground plate in the first conductor plate layer and a first via extending through and electrically coupled to a high voltage plate in the second conductor plate layer. The first ground plate vertically overlaps the high voltage plate and the second insulator layer is different from the first insulator layer.

High voltage passive device structure

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Hsinchu, Taiwan

Dian-Hau Chen