Shanghai Zhaoxin Semiconductor Co., Ltd.

Huawei Technologies Co., Limited

China Academy of Space Technology

Di Hu

Zongpu Qi

Zheng Wang

Wei Zhao

Min Liu

Xiaoyang Li

Jin Yu

Yanliang Liu

Zhen Liu

Fangfang Wu

Qinghua Yan

Lei Meng

Xuehua Han

Yaobing Cao

Baoxiang Sun

Liqing Su

Jixian Qu

Dongzhi Guo

Zhicheng Zhou

Dmytro Kutra

Chuanbing Wang

Lede Qiu

Jungang Yuan

Fuxiang Dong

This application discloses example frequency control methods, frequency controllers, processors, and electronic devices. One example method includes obtaining at least two temperatures of a processor core, where each of the at least two temperatures corresponds to a frequency. A load change mode of the processor core is determined, where the load change mode indicates a change status of a load of the processor core. A target temperature is determined from the at least two temperatures of the processor core based on the load change mode. A frequency of the processor core is adjusted based on the target temperature.

Frequency control method and apparatus

A processing system includes a cache, a host memory, a CPU and a hardware accelerator. The CPU accesses the cache and the host memory and generates at least one instruction. The hardware accelerator operates in a non-temporal access mode or a temporal access mode according to the access behavior of the instruction. The hardware accelerator accesses the host memory through an accelerator interface when the hardware accelerator operates in the non-temporal access mode, and accesses the cache through the accelerator interface when the hardware accelerator operates in the temporal access mode.

Hardware accelerators and access methods thereof

A chipset with a near-data processing (NDP) engine, which uses the NDP engine to perform a command transformation and thereby to generate an input and output (I/O) command to operate a peripheral device connected to the chipset. The chipset further has a traffic control module. The chipset receives a request to operate the peripheral device, and the traffic control module directs the request to the NDP engine to be transformed into the I/O command. The NDP engine may implement a file system, or achieve acceleration of a database or may be operated to cope with a remote direct memory access packet.

Chipset with near-data processing engine

A chipset with a near-data processing (NDP) engine, which uses the NDP engine to perform a command transformation and thereby to generate an input and output (I/O) command to operate a peripheral device connected to the chipset. The chipset further has a traffic control module. A Remote Direct Memory Access (RDMA) packet comes from a remote computer system and is received by the chipset to operate the peripheral device. The traffic control module directs the RDMA packet to the NDP engine to be transformed into the I/O command. The NDP engine is provided to cope with the RDMA packet.

A data center network system and a signal transmission system, where the signal transmission system includes one hub device, at least two switches, multiple colored optical modules, at least two multiplexers/demultiplexers, and at least two servers. The hub device, the at least two switches, the multiple colored optical modules, the at least two multiplexers/demultiplexers, and the at least two servers form a star network topology structure.

Data center network system and signal transmission system

A balancing device, which is configured to balance a first duty cycle of a first accelerator and a second duty cycle of a second accelerator, includes a loading monitor and a loading balancer. The loading monitor is configured to monitor a first busy period of the first accelerator and a second busy period of the second accelerator. The loading balancer calculates the first duty cycle and the second duty cycle according to the first busy period and the second busy period, and moves at least one command queue of the first accelerator and the second accelerator according to the first duty cycle and the second duty cycle, such that the first duty cycle is close to the second duty cycle.

Balancing the loadings of accelerators

A storage device includes a memory unit, an access monitor, and a memory configurator. The memory unit includes a plurality of memory blocks. The access monitor is configured to monitor whether an access mode of the memory unit is a continuous-access mode or a random-access mode, to generate a monitor signal. The memory configurator configures, according to the monitor signal, any of the memory blocks to be either in a cache mode or a SRAM state to generate a configuration signal.

Storage device with dynamic configuration

The invention introduces a method for accelerating compression, performed in a compression accelerator, including: repeatedly executing a loop for determining the longest matched-length between a first string and a second string. Each iteration of the loop includes: obtaining n successive characters from the first string as a source string, wherein n is greater than 1; comparing each character of the source string with all characters of the second string, so as to generate n first-match-results corresponding to the n successive characters of the source string respectively; generating a second-match-result according to the n first-match-results; and determining whether a continuous match of the n successive characters is presented according to the second-match-result. If so, n is added to the matched length and the next iteration of the loop is continued to execute. Otherwise, a matched length is updated and output and the loop is exited.

Methods for accelerating hash-based compression and apparatuses using the same

Growing community of inventors

Beijing, China

Di Hu