Inphi Corporation

Dhruv Jain

Gopal Raghavan

Carl W Pobanz

Jeffrey C Yen

An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a 'normal' mode, and a second output impedance which is greater than the first output impedance when operated in a 'standby' mode. By increasing the drive circuit's output impedance while in &#x2018;standby&#x2019; mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in &#x2018;standby&#x2019; mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.

Output buffer with switchable output impedance

A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKand generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (t) between the toggling of CKand a resulting change at the slave latch's output less than it would otherwise be.

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Woodland Hills, CA, United States of America

Dhruv Jain