International Business Machines Corporation

Dhirendra Dhopeshwarkar

Rafael Graniello Cabezas

Robert G Kovacs

Arthur James Tysor

John Walter Mehl

Mac A Mathis

Scott A Hightower

A method for testing a computer bus using a bridge chip having a freeze-on-error option that enables a computer system's central processing unit (CPU) to recover and continue processing even when the computer bus is not functional. The testing method of the present invention remains transparent to a user and can be accomplished while performing standard diagnostics tests. In general, the present invention injects an input/output (I/O) error into a specific bus slot of the computer bus to test the functionality (such as the error recovery capability) of the bus. The present invention then recovers from the failure condition without having the computer system shutdown or stop working and without having to restart the computer system. More specifically, the method for testing a computer bus according to the present invention includes enabling the freeze-on-error option on the bridge chip, injecting an error into the specified computer bus slot and recovering from the injected error. The error recover capability of the computer bus is determined by examining the status of the bus slots both with the injected error condition and without the injected error condition.

Method for testing a computer bus using a bridge chip having a freeze-on-error option

A computer system with provision for inserting/removing memory cartridges is improved by inhibiting erroneous operation as a result of noise produced on insertion/removal of a memory cartridge. Removable cartridges are connected/disconnected from a cartridge bus which is distinct from the system bus to which all other components are coupled. A controlled isolation is provided between the two buses. An idler routine ensures that in the absence of operator requested tasks the isolation prevents noise on the cartridge bus from reaching the system bus. When the processor executes an instruction (or only selected instructions) the isolation is disabled so that data/instructions can flow to/from the system and cartridge bus.

Systems for inhibiting errors caused by memory cartridge

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Austin, TX, United States of America

Dhirendra Dhopeshwarkar