Xilinx, Inc.

Dhimant Patel

Jeffrey H Seltzer

Carol A Fields

Anthony D Williams

Veena N Kumar

Roberta E Fulton

The notion of global signals (e.g., global set/reset and global tristate) is of significance to programmable logic user throughout the design process. Regardless of whether the HDL designer explicitly describes the use of a global signal, they are present in the implemented device since they are an integral part of the initialization and start-up process. This may lead to mismatches between the Register Transfer Level (RTL) simulation and the timing simulation. While a methodology for verifying the functionality of global signals is available for schematic design entry, none exists for HDL design tools. A verification method for HDL designers is disclosed providing access to all the functionality relating to global networks currently available to the schematic designers and allowing reuse of the testbench without losing HDL code portability.

Method and system for HDL global signal simulation and verification

A method of modeling a pullup device and a pulldown device with delay back annotation in accordance with the VITAL application specific integrated circuit modeling specification. The modeling method comprises the steps of modeling an entity and creating an identity primitive procedure which delays an input signal by a value specified in a timing generic and also preserves the signal shape. The procedure is then used to perform state pre-mapping of the incoming signal to preserve the identity of selected states (including all states). The delayed and pre-mapped signal forms the input to a VITAL state table to model the behavior of the device. The identity primitive procedure is then used to post-map the resulting signal in order to recover the selected states of the input signal. By altering the state pre- and post-mapping tables, either pullup or pulldown, both with delay back annotation may be modeled using the functions and procedures of the VITAL specification.

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Dhimant Patel