International Business Machines Corporation

Globalfoundries Inc.

Dheeraj Sreedhar

Jeffrey Haskell Derby

Robert K Montoye

Steven Paul VanderWiel

Charles D Johnson

Charles Luther Johnson

Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.

Vector cross-compare count and sequence instructions

Methods, systems and computer program products for accelerating sorting of data are provided herein. A computer-implemented method includes retrieving a plurality of cache lines of data from an input buffer, wherein each cache line comprises a plurality of elements, scattering the plurality of elements of each retrieved cache line into a plurality of bins, wherein said scattering comprises using one or more vector instructions, forming a bin cache line in a corresponding one of the plurality of bins, wherein the bin cache line comprises a group of the plurality of elements which were scattered to the corresponding one of the plurality of bins, writing the bin cache line from the corresponding one of the plurality of bins to a memory, and loading the bin cache line from the memory to the input buffer.

In-memory/register vector radix sort

Methods and arrangements for joining data sets. There are accepted: a first data set which forms a table in a relational database, and a second data set which forms a table in a relational database, each of the first and second data sets comprising a key value. Each of the first and second data sets is hashed based on the key value, and are thereupon sorted based on the key value. The sorted first and second data sets are joined with one another based on the key value. Other variants and embodiments are broadly contemplated herein.

Sort-merge-join on a large architected register file

In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.

High-performance hash joins using memory with extensive internal parallelism

Methods, systems, and articles of manufacture for merging and sorting arrays on a processor are provided herein. A method includes splitting an input array into multiple sub-arrays across multiple processing elements; merging the multiple sub-arrays into multiple vectors; and sorting the multiple vectors by comparing and swapping one or more vector elements among the multiple vectors.

Merging and sorting arrays on an SIMD processor

In one embodiment, a method includes receiving a signal having communication data from two or more mobile devices, each identifiable by an associated pseudonoise sequence. A first mobile device is identifiable by a first pseudonoise sequence. Two or more samples of the received signal are stored in an input register. A segment of the first pseudonoise sequence is stored as a bit vector in a second register. The SIMD instruction is processed, by an SIMD processor, to produce correlation values associated with the segment of the first pseudonoise sequence and the samples of the received signal. Processing the SIMD instruction includes distributing the segment of the first pseudonoise sequence, as a bit vector, across two or more lanes of the SIMD processor. The processing contributes to despreading the received signal, and an output of the processing includes at least a portion of the communication data from the first mobile device.

Correlating pseudonoise sequences in an SIMD processor

Methods and arrangements for parallelizing turbo encoding computations. At least one processor is provided. Turbo encoding computations are split into first and second parts. Using at least one processor, the computations of the first part are performed. Thereafter, using the at least one processor, the computations of the second part are performed, the second part correcting output provided by the computations of the first part. One of the first and second parts comprises computations performed in parallel and the other of the first and second parts comprises computations performed not in parallel. Other variants and embodiments are broadly contemplated herein.

Growing community of inventors

Bengaluru, India

Dheeraj Sreedhar