Intel Corporation

Texas Instruments Corporation

Dheeraj Kumar Shetty

Karthik Subburaj

Karthik Ramasubramanian

Ramnarayanan Ram Muthukaruppan

Shailesh Joshi

Tarun Mahajan

Shankar Narayanamoorthy

Anand Gadiyar

Saurabh Anmadwar

Madhuban Kishor

Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.

Methods and apparatus to compensate for radar system calibration changes

An active current source load of a fully differential amplifier which is converted into a transconductance (g) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gat dc and becomes g+(g+g) at high frequency which triples the UGB when g=g.

Low-power and area-efficient gain-bandwidth tripler amplifier

An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

Time-to-digital converter

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Bengaluru, India

Dheeraj Kumar Shetty