Intel Corporation

Dheemanth Nagaraj

Rahul Pal

Manoj K Arora

Sailesh Kottapalli

Henk G Neefs

Ganesh Kumar

Gregory S Averill

Vincent R Freytag

Eric R Delano

Robert G Blankenship

Dheeraj R Subbareddy

Devadatta V Bodas

Md Altaf Hossain

Ankireddy Nalamalpu

Russell Jerome Fenger

Mahesh K Kumashikar

Anshuman Thakur

Atul Maheshwari

James Steven Burns

Baskaran Ganesan

Suresh Sugumar

Eric R DeLano

Sundaravarathan R Iyengar

Feranak Nelson

Rajesh Vivekanandham

The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

Three-dimensional stacked programmable logic fabric and processor design architecture

In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

Extending a cache coherency snoop broadcast protocol with directory information

Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions. Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.

Protocol for conflicting memory transactions

Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.

Efficient frequency boost operation

Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.

Memory mirroring and migration at home agent

In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.

Controllably exiting an unknown state of a cache coherency directory

Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.

Home agent data and memory management

Growing community of inventors

Bengaluru, India

Dheemanth Nagaraj