Tata Consultancy Services Limited

Tata Consultancy Services Lmited

Dhaval Shah

Manoj Karunakara Nambiar

Mahesh Damodar Barve

Sunil Anant Puranik

Manoj Karunakaran Nambiar

Ishtiyaque Shaikh

Arpan Pal

Sounak Dey

Swapnil Shashikant Rodi

Subhasri Duttagupta

Piyush Manavar

Mukund Kumar

Sharyu Vijay Mukhekar

Meripe Ajay Kumar

This disclosure relates generally to a method and a system for computing using a field programmable gate array (FPGA) neuromorphic architecture. Implementing energy efficient Artificial Intelligence (AI) applications at power constrained environment/devices is challenging due to huge energy consumption during both training and inferencing. The disclosure is a FPGA architecture based neuromorphic computing platform, the basic components include a plurality of neurons and memory. The FPGA neuromorphic architecture is parameterized, parallel and modular, thus enabling improved energy/inference and Latency-Throughput. Based on values of the plurality of features of the data set, the FPGA neuromorphic architecture is generated in a modular and parallel fashion. The output of the disclosed FPGA neuromorphic architecture is the plurality of output spikes from the neuron, which becomes the basis of inference for computing.

Field programmable gate array (FPGA) based neuromorphic computing architecture

A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.

Low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware

A method and system of a re-assembly middleware in FPGA for processing TCP segments into application layer messages is disclosed. In recent years, the communication speed in digital systems has increased drastically and thus has brought in a growing need to ensure a good/high performance from the FPGA services. The disclosure proposes a re-assembly middleware in the FPGA for processing TCP segments into application layer messages at a pre-defined frequency for a good/high performance. The pre-defined frequency is a high frequency performance feature of the re-assembly middleware, wherein the FPGA's implementation frequency is at atleast 300 MHz based on a memory optimization technique. The memory optimization technique includes several strategies such registering an output and slicing memories.

Re-assembly middleware in FPGA for processing TCP segments into application layer messages

Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.

Multiple field programmable gate array (FPGA) based multi-legged order transaction processing system and method thereof

Systems and methods for benchmark based cross platform service demand prediction includes generation of performance mimicking benchmarks that require only application level profiling and provide a representative value of service demand of an application under consideration on a production platform, thereby eliminating need for actually deploying the application under consideration on a production platform. The PMBs require only a representative estimate of service demand of the application under test and can be reused to represent multiple applications. The PMBs are generated based on a skeletal benchmark corresponding to the technology stack used by the application under test and an input file generated based on application profiling that provides pre-defined lower level method calls, data flow sequences between multi-tiers of the application under test and send and receive network calls made by the application under consideration.

Systems and methods for benchmark based cross platform service demand prediction

Growing community of inventors

Thane West, India

Dhaval Shah