Freescale Semiconductor,inc.

Astrowatt, Inc.

Other

Dharmesh Jawarani

Leo Mathew

Mark Douglas Hall

Mehul D Shroff

Ramachandran Muralidhar

Edward Outlaw Travis, Jr

Tushar Praful Merchant

Rode R Mora

John R Alvis

John E Moore

Michael G Harrison

Marius K Orlowski

Olubunmi O Adetutu

Chun-Li Liu

Tab Allen Stephens

Vishal P Trivedi

Michael D Turner

Byoung W Min

Konstantin V Loiko

Nigel Graeme Cave

Chong-Cheng Fu

Andrew G Nagy

David C Wang

Ross Edward Noble

Michael Rendon

Randy W Cotton

A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

Phase change memory cell with heater and method therefor

A method for making a semiconductor device is provided by (a) providing a substrate () having first () and second () gate structures thereon; (b) forming an underlayer () over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer () over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.

Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack

A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.

Method of forming an electronic device using a separation technique

A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

A semiconductor fabrication process includes forming a gate electrode () overlying a gate dielectric () overlying a semiconductor substrate () of a wafer () and a liner dielectric layer () including vertical portions () adjacent sidewalls of the gate electrode and horizontal portions () overlying an upper surface of the semiconductor substrate (). A spacer () is formed adjacent a vertical portion () and overlying a horizontal portion () of the liner dielectric layer (). After forming the spacer (), exposed portions of the liner dielectric layer () are removed to form a liner dielectric structure () covered by the extension spacer (). The extension spacer () is then etched back to expose or uncover extremities of the liner dielectric structure (). Prior to etching back the spacer (), a metal () may be sputtered deposited over the wafer () preparatory to forming a silicide (). After the etch back the wafer () may be dipped in piranha solution and cleaned with an RF sputter () of argon.

Semiconductor fabrication process including silicide stringer removal processing

A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.

SOI semiconductor device with body contact and method thereof

A method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material. The method can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating a semiconductor layer and the metallic layer from the substrate, wherein the semiconductor layer is a portion of the substrate. In a particular embodiment, the separation-enhancing species can be incorporated into a metallic layer and moved into the substrate, and in particular embodiment, the separation-enhancing species can be implanted into the substrate. In still another embodiment, both the techniques can be used. In a further embodiment, a dual-sided process can be performed.

Method of forming an electronic device using a separation-enhancing species

A method for making a semiconductor structure () includes providing a wafer with a structure () having a sidewall, forming a sidewall spacer () adjacent to the sidewall, and forming a layer of material () over the wafer including over the sidewall spacer and over the structure having the sidewall. The method further includes etching the layer, wherein the etching (i) leaves at least portions of the sidewall spacer exposed and (ii) leaves a portion of the layer located over the structure having a sidewall. The portion of the layer located over the structure having a sidewall is reduced in thickness by the etching. Subsequent to etching the layer, the method includes removing the sidewall spacer.

Method of making a semiconductor structure utilizing spacer removal and semiconductor structure

A semiconductor process and apparatus provide a T-shaped structure () formed from a polysilicon structure () and an epitaxially grown polysilicon layer () and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi) in at least the upper region () of the T-shaped structure () without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

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A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier 'curtains' on sidewalls of the source/drain recesses. A metal layer is deposited wherein the metal layer contacts a semiconductor within the recess. The wafer is annealed to form a silicide selectively. The diffusivity of the metal with respect to the barrier structure material is an order of magnitude less than the diffusivity of the metal with respect to the semiconductor material. The etched recesses may include re-entrant sidewalls. The metal layer may be a nickel layer and the barrier layer may be a titanium nitride layer. Silicon or silicon germanium epitaxial structures may be formed in the recesses overlying the semiconductor substrate.

Diffusion barrier for nickel silicides in a semiconductor fabrication process

A semiconductor process and apparatus provide a polysilicon structure () and source/drain regions () formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions () using a first metal (e.g., cobalt). After forming sidewall spacers (), a second metal (e.g., nickel) is used to form second silicide regions in the polysilicon, source and drain regions () to reduce encroachment by the second silicide in the source/drain () and to reduce resistance in the polysilicon structure caused by agglomeration and voiding from the first silicide ().

Dual metal silicide scheme using a dual spacer process

A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.

Method for selective removal of a layer

A semiconductor process and apparatus provide a T-shaped structure () formed from a polysilicon structure () and polysilicon spacers () and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi) in at least the upper region () of the T-shaped structure () without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.

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Round Rock, TX, United States of America

Dharmesh Jawarani