Avago Technologies General IP (singapore) Pte. Ltd.

Lsi Corporation

Avago Technologies International Sales Pte. Limited

Dharmendra Kumar Rai

Rahul Sahu

Ankur Goel

Rasoju Veerabadra Chary

Mohammed Rahim Chand Seikh

Donald Albert Evans

Dennis E Dudeck

Ronald James Wozniak

Richard John Stephani

Rajiv Kumar Roy

Disha Singh

Manish Umedlal Patel

Mohit Gupta

Jeffrey Charles Herbert

Bijan Kumar Ghosh

Sumith Kaippalathingal Soman

Biswa Bhusan Sahoo

Vipin Aryamvalli

An accelerator circuit is provided that includes an inverter chain having an input coupled to a data line and a sense circuit having inputs coupled to an output of the inverter chain and the data line. The sense circuit is configured to sense a rise toward a supply voltage on the data line or a fall toward a ground voltage on the data line. The accelerator circuit further includes an amplify circuit having inputs coupled to outputs of the sense circuit and an output coupled to the data line, where the amplify circuit is configured to amplify the data line toward the supply voltage or toward the ground voltage based on amplify enable signals output by the sense circuit.

Read accelerator circuit

Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal.

Systems and methods for voltage level shifting in a device

In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking bit line (TBL) and/or a clock signal (e.g., GCLKB)) transitions from one voltage level to another voltage level. A process-and-temperature-dependent bias circuit is provided to control the charge-injection pull-up transistor. The bias circuit causes the charge-injection pull-up transistor to adjust the discharge rate or transition rate of the signal line to compensate for timing delays caused by process or temperature variations.

Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement

A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.

Memory sense amplifier and column pre-charger

A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.

Memory banks with shared input/output circuitry

In one embodiment, a self-timed, dual-rail SRAM includes a self-timing circuit having a logic gate that is powered by voltage VDD and configured to receive a fire-sense-amplifier timing signal and to produce a VDD-domain sense-amplifier-enable signal SOELV. The self-timing circuit includes an inverting level-shifter having complementary N-type and P-type transistors connected in series between voltage VDDA and ground. The N-type transistor's gate is connected to signal SOELV, and both transistors' drain terminals are connected together to produce output signal SOEHVB. The inverting level-shifter also includes two series-connected P-type transistors connected (i) between supply voltage VDDA and the output and (ii) in parallel with the first P-type (pull-up) transistor. An inverter is connected between the output node and the control terminal of one of the series transistors, and the other series-transistor's gate is connected to signal SOELV. Thus, the series transistors provide a rapid latching and latch-breaking function.

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail SRAM memories

Word line assist circuits are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a pair of word lines that traverse the memory cell array for selecting memory cells. The SRAM device further includes a pair of word line drivers, each coupled to one of the word lines. The SRAM device further includes a word line assist circuit coupled to the pair of word lines that receives an enable signal. Responsive to receiving the enable signal, the word line assist circuit assists the first word line driver and the second word line driver in transitioning their respective word lines from a logic level zero to a logic level one in response to a voltage differential between the word lines.

Differential latch word line assist for SRAM

A write-tracking circuit for a writable memory array has one or more dummy memory cells and is configured to write different values to the one or more dummy memory cells. Durations of pulses applied to word lines of the memory array during write operations are controlled based on durations of writing the different values to the one or more dummy memory cells. In at least some embodiments, the write-tracking circuit is configured to write the different values to the one or more dummy memory cells during a single write operation. In at least some embodiments, the write-tracking circuit is configured to write the different values to at least one of the one or more dummy memory cells during different write operations.

Write-tracking circuitry for memory devices

A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Growing community of inventors

Bengaluru, India

Dharmendra Kumar Rai