Intel Corporation

Nxp B.v.

Synopsys, Inc.

Dharmaray Nedalgi

Karthik Ns

Amit Kumar Srivastava

Vani Deshpande

Prasad Bhilawadi

Leonhard Heiss

Raghavendra Devappa Sharma

Jayarama Ubaradka

Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

Back power protection circuit

An apparatus is provided which comprises: a dual stack voltage driver, wherein the dual stack voltage driver comprises a first stack of transistors, and a second stack of transistors; and one or more feedback transistors each coupled to a transistor of the second stack of transistors.

Apparatus and method for over-voltage protection

An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.

Aging tolerant apparatus

State definition and retention circuits are described. In one embodiment, a circuit includes two cross-connected PMOS transistors, first, second, and third NMOS transistors coupled to the PMOS transistors, an inverter circuit, and an output transistor connected to the PMOS transistors and to an output terminal of the circuit. The second NMOS transistor is connected to an input terminal of the circuit. A drain terminal and a gate terminal of the third NMOS transistor are connected to gate terminals of the PMOS transistors. The inverter circuit is coupled to the first and second NMOS transistors and to the input terminal. The inverter circuit is connected between a first power supply and a first base voltage. The PMOS transistors, the NMOS transistors, and the output transistor are connected between a second power supply and a second base voltage. Other embodiments are also described.

State definition and retention circuit

An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (V), a first node (A) and a second node (B), wherein the second node (B) is coupled to an input of a receiver (R). The high-voltage tolerant circuit furthermore comprises a first NMOS transistor (N) and a first PMOS transistor (P) coupled in parallel between the input terminal and the second node(B). Furthermore, a second PMOS transistor (P) is coupled between the input terminal and node A and a second NMOS transistor is coupled with one of its terminals to the first node. The gate of the first NMOS transistor (N) is coupled to a supply voltage (VDDE). The gate of the first PMOS transistor (P) is coupled to the first node (A). The gate of the second NMOS transistor (N) and the gate of the second PMOS transistor (P) are coupled to the supply voltage (VDDE).

Electronic device with a high voltage tolerant unit

A high voltage tolerant bus holder circuit and method of operating the bus holder circuit utilizes first and second control transistors connected in parallel between a control terminal of a pull-up transistor and a bus. The first control transistor is used to turn on the pull-up transistor during a pull-up mode of operation. The second control transistor is used to turn off the pull-down transistor when a voltage on the bus exceeds a threshold.

High voltage tolerant bus holder circuit and method of operating the circuit

The invention relates to a CMOS input circuit for receiving low-swing input signals, which is an alternative to the CMOS input circuits as known from the prior art. The CMOS input circuit according to the invention comprises a leveling circuit (LC) that is constructed for arranging, under control of a voltage associated with an output voltage of a CMOS input stage (Inv), a leveling transistor (M) which is located in a supply path of the CMOS input stage (Inv), (i) as a forward-biased diode-connected transistor for regulating the voltage on a source of the CMOS input stage (Inv) for reducing the gate-source voltage of a switching transistor (M, M) in the CMOS input stage (Inv), when an input voltage of the CMOS input circuit assumes a level associated with a first logical level causing the switching transistor (M, M) to be switched off, and (ii) as a conductive path when the input voltage assumes a level associated with a second logical level causing the switching transistor (M, M) to be switched on. The invention also relates to an Input-Output circuit, an electronic circuit and a semiconductor device comprising such CMOS input circuit. The invention provides an alternative to known CMOS input circuit that make use of a diode-connected transistor that is short-circuited in case of one of the input voltage levels. An advantageous embodiment of the invention incorporates a positive feedback mechanism that makes the circuit more suitable for low supply voltages.

Low-swing CMOS input circuit

An electronic circuit is provided comprising an input (V) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M) is coupled between a second node (tp) and the output (V). The third transistor (M) is coupled between the first node (tn) and the output (V). The fourth transistor (M) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M). The first and second reference voltage generating units (RD, RC) generate a reference voltage according to at least one of the logic states of the first, second, third or fourth transistor (M-M).

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Bengaluru, India

Dharmaray Nedalgi