Intel Corporation

Dharma Teja Vooturi

Subramaniam M Maiyuran

Varghese George

Dipankar Das

Naveen K Mellempudi

Jorge E Parra

Chandra S Gurram

Sasikanth Avancha

Ashutosh Garg

Yan Li

Shubra Marwaha

Supratim Pal

Chunhui Mei

Wei Xiong

Durgesh Borkar

Yongsheng Liu

Mike MacPherson

Fangwen Fu

Sabareesh Ganapathy

An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.

Utilizing structured sparsity in systolic arrays

A processing apparatus is described herein that includes a general-purpose parallel processing engine comprising a matrix accelerator including one or more systolic arrays, at least one of the one or more systolic arrays comprising multiple pipeline stages, each pipeline stage of the multiple pipeline stages including multiple processing elements, the multiple processing elements configured to perform processing operations on input matrix elements based on output sparsity metadata. The output sparsity metadata indicates to the multiple processing elements to bypass multiplication for a first row of elements of a second matrix and multiply a second row of elements of the second matrix with a column of matrix elements of a first matrix.

Systolic array having support for output sparsity

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Dharma Teja Vooturi