Qlogic Corporation

Cavium, Inc.

Dharma Konda

Rajendra R Gandhi

Charles Micalizzi, Jr

Ben Hui

Chandru M Sippy

Bruce Anthony Klemin

Kuangfu David Chu

Sanjaya Anand

Kathy K Caballero

James D Huey

Frank W Campbell

Chuong HoangMinh Pham

Tuan A Doan

Mohana S Devarajan

Sanak H Ream

Paul R Magsino

Ashish Bhargava

Cam Le

Methods and systems for generating interrupts are provided. One method includes maintaining an in-pointer array by a response direct memory access (DMA) module of an adapter indicating that a message has been posted at a host memory of a host system coupled to the adapter for sending and receiving data using a network; updating an out-pointer array at the response DMA module by a host system processor, after the host system processor reads the message posted at the host memory; receiving event information by a hardware based, interrupt module of the response DMA module, the interrupt module using the event information and information stored at an interrupt array to determine that an interrupt is to be generated for the host processor; and generating the interrupt for the host processor by the interrupt module, without using an adapter processor.

Methods and systems for generating interrupts by a response direct memory access module

Methods and systems for a device coupled to a computing device are provided. As an example, one method includes receiving a request for processing an address list control block (ALCB) by an ALCB offload engine of an adapter coupled to a computing device; determining by the ALCB offload engine if the ALCB is located at a cache managed by a cache controller of the ALCB engine; forwarding the ALCB to an address computation module that determines an address of a memory location of the computing device, where the ALCB stores the address of the memory location in an address list; generating a direct memory access (DMA) request to retrieve the ALCB from an adapter memory, when the ALCB is not located at the cache; and storing the ALCB at the cache, after the ALCB is received in response to the DMA request.

Methods and systems for managing address list control blocks

Methods and systems for routing control blocks is provided. One method includes receiving a control block from a computing device at an adapter having a plurality of hardware engines for processing control blocks, where the control blocks are to read data, write data, obtain status for an input/output request and perform a management task; evaluating the control block by the adapter to determine that the control block is a continuation control block for data transfer using more than one control block; is a direct route control block for a specific hardware engine; or is for a management task; routing the control block to a same hardware engine when the control block is a continuation control block; and routing the control block to a master hardware engine from among the plurality of hardware engines, when the control block is for the management task.

Methods and systems for control block routing

Methods and systems for DMA operations are provided. A plurality of control blocks are stored at a memory of a receive module of a device coupled to a computing device, where the control blocks store information regarding data packets stored at a receive buffer accessible to the receive module. At least a first control block and a second control block are retrieved from the memory; and a first DMA register set is assigned to the first control block and a second DMA register set is assigned to the second control block. The first control block and the second control block are simultaneously pre-processed to configure the first DMA register set and the second DMA register set.

Systems and methods for managing direct memory access operations

A system comprising a plurality of virtual machines executed by a computing system; and an adapter; wherein the adapter includes a direct memory access (DMA) module for transferring control blocks to and from a computing system memory to an adapter memory, where the computing system memory has dedicated memory locations for each virtual machine to place the control blocks and the adapter memory has dedicated memory locations for storing the control blocks generated by each of the plurality of virtual machines.

System and methods for using a DMA module for a plurality of virtual machines

A system is provided. The system comprises a plurality of virtual machines executed by a computing system for sending and receiving information; and an adapter presented to the plurality of virtual machines as a shared hardware resource; wherein the adapter includes a direct memory access (DMA) module that is used for transferring control blocks to and from a computing system memory to an adapter memory, where the computing system memory has dedicated memory locations for each virtual machine to place the control blocks and the adapter memory has dedicated memory locations for storing the control blocks generated by each of the plurality of virtual machines; wherein the DMA module stores a context for each virtual machine that includes a computing system memory address assigned to each of the virtual machine and a quality of service entry that is used to limit a number of available control blocks that are transferred for a virtual machine at any given time when a control block from another virtual machine is available and there is storage space available to store the available control block for the other virtual machine.

A host bus adapter ('HBA') is provided with a programmable trace logic that can be enabled or disabled by firmware running on the HBA and if enabled can receive trace information from at least one processor, which is stored in a local memory buffer controlled by a local memory interface. A receive and transmit path processor data is traced and stored in the local memory buffer. The trace logic includes an arbitration module that receives trace data from plural sources and the trace data is stored in a first in first out based buffer before being sent to a direct memory access arbiter module and then to an external memory. Trace data as stored in the external memory includes a trace data source identity value, and a time stamp value indicating when data was collected.

Method and system for efficiently recording processor events in host bus adapters

Method and system for testing application specific integrated circuit using a tester is provided. The method includes measuring output data timing values of the application specific integrated circuit with respect to a tester cycle in a first pass; measuring first strobe timing value and second strobe timing value with respect to the tester cycle in a second pass; and calculating data set-up timing values and data hold timing values with respect to the first strobe and the second strobe, using the output data timing values measured in the first pass and the first strobe timing value and second strobe timing value measured in the second pass. The tester includes an input vector generator that generates input data for the application specific integrated circuit that is coupled to a data processing unit that calculates data set-up timing values and data hold timing values.

Method and system for testing integrated circuits

A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code ('CRC') mode from amongst append, validate and keep, and validate and remove mode. If the append mode is selected, then CRC is appended after each data block boundary. A CRC seed value is incremented for each data block providing a unique CRC value for each data block. If validate and keep mode is selected, then CRC accompanying any data is compared to CRC that may have been accumulated. If validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent out. The system includes CRC logic that allows firmware running on an adapter to select one of plural CRC modes including append, validate and keep, and validate and remove mode.

Method and system for providing data integrity in storage systems

An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Growing community of inventors

Aliso Viejo, CA, United States of America

Dharma Konda