Texas Instruments Corporation

Mediatek Singapore Pte. Ltd.

Dharin Nayeshbhai Shah

Steven Craig Bartling

Charles M Branch

Girishankar Gurumurthy

Vinod J Menezes

Clive D Bittlestone

Sharad Kumar Gupta

Nagaraj Narasimh Savithri

Sumanth Katte Gururajarao

Vish Visvanathan

Pavan Vithal Torvi

Manish Trivedi

Wah Kit Loh

Uming U Ko

Anand Seshadri

James Robert Hochschild

Parvinder Kumar Rana

Rolf Lagerquist

Senthil Kumar Sundaramoorthy

Graham McLeod Barr

Sanchayan Sinha

Ajith Subramonia

Achin Grover

Bindu Prabhakar Rao

A self-time circuitry is coupled to a first power rail to receive a first voltage and a second power rail to receive a second voltage. The self-time circuitry includes a tracking control circuit which generates a first tracking signal at the first voltage and a second tracking signal at the second voltage. In response to a memory access request, a first number of dummy discharge cells (DDCs) in a first DDC group are activated according to the first tracking signal to discharge a dummy bit line (DBL), and a second number of DDCs in a second DDC group are activated according to the second tracking signal to discharge the DBL. The DBL mimics operations of a bit line in a memory cell array and the DDCs in the first DDC group and the second DDC group mimic operations of bit cells in the memory cell array.

Self-time scheme for optimizing performance and power in dual rail power supplies memories

Control circuits for memory devices are described. The control circuits may be configured such that the duration of the pulses delivered to the sense amplifiers increases with increasing parasitic RC delays. That is, the larger the parasitic RC delay along a line connecting a drive circuit to the sense amplifiers, the larger the duration of the pulses delivered. In some embodiments, a feedback line may be inserted between the end of the output signal line and the drive circuit to route the control pulses back to the drive circuit. The drive circuit may be arranged such that the duration of the pulses with which the sense amplifiers are driven depends on the delay experienced along the feedback line. In this way, the longer the RC delay arising along the feedback line, the larger the durations of the pulses.

Circuits for pulse-width control in memory devices and related methods

A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.

Read-current and word line delay path tracking for sense amplifier enable timing

Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.

Error prediction in logic and memory devices

A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality

Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.

Improving routability of integrated circuit design without impacting the design area

A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.

Contact resistance and capacitance for semiconductor devices

Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).

Generation of standard cell library components with increased signal routing resources

A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and scan data into a storage element contained in the memory cell. The use of separate clock signals permits transmission of scan data and functional data via separate paths, thereby eliminating additional circuitry that are otherwise needed to multiplex such scan and functional data through a same path. The absence of such additional circuitry reduces the time delays from input to output. The structure of the memory cell provided also permits easy addition of logic functions without substantially affecting operating speeds.

Cell supporting scan-based tests and with reduced time delay in functional mode

In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.

Slave latch controlled retention flop with lower leakage and higher performance

A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch includes dedicated functional data and scan data output ports. The digital storage element operates in a functional mode and in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.

Digital storage element architecture comprising dual scan clocks and gated scan output

An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

Performance and area scalable cell architecture technology

A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.

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Bengaluru, India

Dharin Nayeshbhai Shah