International Business Machines Corporation

Globalfoundries Inc.

Dhani Reddy Sreenivasula Reddy

Krishnan Santhana Rengarajan

Eswararao Potladhurthi

Dinesh Chandra

Venkatraghavan Bringivijayaraghavan

Vinay Bhat Soori

Md Nadeem Iqbal

An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Tunable negative bitline write assist and boost attenuation circuit

The present disclosure relates to a structure which includes at least one keeper circuit which is configured to hold data to a precharged state during a first operation and be disabled during a second operation.

Data dependent keeper on global data lines

The present disclosure relates to a structure which includes an assist circuit which is configured to add a boost voltage using a common boost logic device for both a read logic circuit and a write logic circuit of the assist circuit.

Common boosted assist

Tunable negative bit line write assist and boost attenuation circuit

A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.

Bit line strapping scheme for high density SRAM

A memory circuit configured for reducing dynamic read power is disclosed that includes a first read global bit line connected to a first sense amp and a second read global bit line connected to a second sense amp. The second read global bit line is adjacent to the first read global bit line. The memory circuit further includes a third read global bit line and logic circuitry connected to the first read global bit line, the second read global bit line, and the third read global bit line. The logic circuitry is configured to determine when both the first read global bit line and the second read global bit line are evaluated as in a high state, and in response to the determining, toggle the third read global bit line to the high state.

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Proddatur, India

Dhani Reddy Sreenivasula Reddy