Intel Corporation

Intel Ndtm US LLC

Dhanashree R Kulkarni

Rezaul Haque

Bayan Nasri

Ali Khakifirooz

Shantanu R Rajwade

Tzu-Ning Fang

Narayanan Ramanan

Matin Amani

Ahsanur Rahman

Netra Mahuli

Seong Je Park

A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.

Memory cell sensing circuit with adjusted bias from pre-boost operation

Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.

Staggered active bitline sensing

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El Dorado Hills, CA, United States of America

Dhanashree R Kulkarni