Changxin Memory Technologies, Inc.

Beijing Superstring Academy of Memory Technology

Deyuan Xiao

Guangsu Shao

Yunsong Qiu

Weiping Bai

Joonsuk Moon

Semyeong Jang

Xingsong Su

Jo-lan Chin

Youming Liu

Yi Jiang

Yong Yu

Minki Hong

Kyongtaek Lee

Yuhan Zhu

Juanjuan Huang

Minmin Wu

Kanyu Cao

Jie Bai

Yiming Zhu

Lixia Zhang

A semiconductor structure includes a substrate and a conductive structure located above the substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart from each other and extend in a first direction. Lengths of the first conductive structures and lengths of the second conductive structures vary in steps. The lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures vary in steps. The first conductive structures and the second conductive structures form Word Lines (WLs).

Semiconductor structure and manufacturing method therefor, and memory

The semiconductor structure includes a first capacitive structure located on a substrate and first support columns. A plurality of first support columns are disposed on the substrate in parallel and spaced apart from each other, and are located in a same plane parallel to the substrate. The first capacitive structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer. The semiconductor structure further includes a plurality of first segmentation trenches. The first segmentation trenches divide the first capacitive structure into a plurality of capacitors. A first insulation layer is disposed between the corresponding first lower electrode layers of the adjacent capacitors. The corresponding first upper electrode layers of the adjacent capacitors are electrically connected to each other.

Semiconductor structure and method for manufacturing semiconductor structure

Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate; a semiconductor pillar located on the substrate and a gate pillar located on the semiconductor pillar, in which the semiconductor pillar and the gate pillar both extend in a direction perpendicular to a plane of the substrate; a first word line extending in a first direction parallel to the plane of the substrate and surrounding the semiconductor pillar; and a semiconductor layer located above the semiconductor pillar and at least surrounding a sidewall of the gate pillar.

Semiconductor structure

Embodiments provide a semiconductor structure and a fabrication method thereof, which relate to the field of semiconductor technology. The method for fabricating a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array in the substrate; and forming a gate arranged around each of the active pillars, where a projection of the gate on the active pillar covers a channel region of the active pillar. Along a direction perpendicular to the substrate, the gate includes a first conductive layer and a second conductive layer sequentially arranged in a stack, and a work function of the first conductive layer is different from a work function of the second conductive layer.

Semiconductor structure and fabrication method thereof

The present disclosure provides a transistor and a manufacturing method thereof, and a memory, relates to the technical field of semiconductors. The transistor includes: a channel, wherein an accommodation space is formed therein; a gate, provided with a first end and a second end that are opposite, wherein the first end of the gate is located inside the accommodation space, and the second end of the gate is located outside the accommodation space; a dielectric layer, located between the gate and a channel, insulating and isolating the gate and the channel; a source, provided at one end of the channel; and a drain, provided at the other end of the channel, wherein the drain and the source are arranged at intervals along a length direction of the channel, and the source, the drain, and the channel are each made of a semiconductor material.

Transistor and manufacturing method thereof, and memory

A three-dimensional memory and a method for forming the same are provided. The three-dimensional memory includes a substrate, a plurality of word lines and a plurality of lead lines. The word lines are located on the substrate. Each of the word lines extends in a first direction, and includes a first end and a second end opposite to the first end along the first direction. The lead lines are located on the substrate and are connected to the word lines in one-to-one correspondence. There are at least two adjacent word lines, in which the lead line connected to one of the at least two adjacent word lines is located at the first end, and the lead line connected to the other one of the at least two adjacent word lines is located at the second end.

Three-dimensional memory and method for forming same

A method for forming a semiconductor device includes the following operations. A stacked structure is provided, which includes a substrate, and sacrificial layers and semiconductor layers alternately stacked on surface of the substrate. Multiple first grooves and semiconductor pillars extending in first direction are included in the sacrificial layers and the semiconductor layers. Word line pillars are formed in second direction, intersect with the semiconductor pillars and surround the semiconductor pillars. Sources and drains are formed respectively on either side of the semiconductor pillars surrounded by the word line pillars by an epitaxial growth process. Bit lines are formed on a side of the sources or the drains, are connected with same, and extend in third direction. The first, second and third directions are pairwise perpendicular. Capacitors are formed on a side of the sources or the drains where the bit lines are not formed to form a semiconductor device.

Method for forming semiconductor device and semiconductor device

The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a forming method thereof. The forming method of a semiconductor device includes: providing a substrate; etching the substrate to form first recesses and second recesses located below the first recesses and communicating with the first recesses; forming a bit line in the second recesses; forming, at bottoms of the first recesses, an isolation layer covering the bit line; enlarging an inner diameter of the first recess above the isolation layer; and forming a gate layer on a sidewall of the first recess whose inner diameter is enlarged.

Semiconductor device having bottom bit line and narrow channel, and forming method thereof

A method for manufacturing a semiconductor structure includes providing a substrate; forming mutually parallel first trenches extending along a first direction in the substrate and first isolation structures filling the first trenches; forming mutually parallel second trenches extending along a second direction in the substrate and in the first isolation structures, the first and second trenches dividing the substrate to form active pillars, and a depth of the second trenches being less than that of the first trenches; forming second isolation structures alternately arranged with the first isolation structures along the second direction at bottoms of the second trenches, top surfaces of the second isolation structures being lower than bottom surfaces of the second trenches located in the first isolation structures; forming bit line structures on the second isolation structures; and forming word line structures above the bit line structures.

Semiconductor structure, method for manufacturing same and memory

Embodiments relate to a three-dimensional semiconductor structure and a formation method thereof. The three-dimensional semiconductor structure includes: a substrate; and a device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows.

Three-dimensional semiconductor structure and formation method thereof

Disclosed in the embodiments of the present disclosure are a semiconductor structure and method for manufacturing same, and a memory. The semiconductor structure includes: a plurality of first active columns arranged in an array along a first direction and a second direction, a plurality of first electrodes located in first grooves arranged at intervals, a plurality of first dielectric layers, and a second electrode covering surfaces of the first dielectric layers. The first direction and the second direction are perpendicular to the extension direction of the first active column, and the first direction is intersected with the second direction. Each first electrode covers a side wall of one of the first active columns. Each first groove surrounds a surface of each first active column. Each first dielectric layer covers the side wall of one of the first electrodes and a bottom of a gap between two adjacent first electrodes.

Semiconductor structure and method for manufacturing same, and memory

Embodiments relate to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a substrate and a semiconductor layer positioned above the substrate, where the semiconductor layer includes first trenches spaced along a first direction, the first direction being a direction parallel to a top surface of the substrate; forming, in the semiconductor layer, an isolation trench positioned below the first trenches, where the isolation trench extends along the first direction and continuously communicates with the first trenches; forming a first spacer at least positioned in the isolation trench; and forming a capacitor above the first spacer. The semiconductor structure and the formation method thereof reduce electric leakage between the substrate and the capacitor, thereby improving electrical performance of the semiconductor structure.

Semiconductor structure for DRAM having a pillar lower electrode and formation method thereof

A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.

Semiconductor structure including a plurality of semicondcutor pillars and bit line isolation trenches and method for forming same

A semiconductor structure includes: a substrate, a first gate structure, and a second gate structure. The substrate includes: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and a second semiconductor pillar and a third semiconductor pillar extending in the vertical direction, the second and third semiconductor pillars are provided at a top of each first semiconductor pillar. The first gate structure is arranged in a middle region of the first semiconductor pillar and surrounds the first semiconductor pillar. The second gate structure is arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and includes a first ring structure and a second ring structure. The first ring structure surrounds the second semiconductor pillar, and the second ring structure surrounds the third semiconductor pillar.

Semiconductor structure with semiconductor pillars and method for manufacturing same

A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple semiconductor pillars, memory structures, and multiple transistors. The multiple semiconductor pillars are arrayed along a first direction and a second direction. Each semiconductor pillar includes a first portion and a second portion on the first portion. The memory structure includes a first electrode layer, a dielectric layer and a second electrode layer. The first electrode layers cover sidewalls of the first portions and are located in first filling regions arranged at intervals. Each first filling region surrounds a sidewall of the first portion. The dielectric layers cover at least surfaces of the first electrode layers. The second electrode layers cover surfaces of the dielectric layers. Channel structures of the transistors are located in the second portions, and extend in a same direction as the second portions.

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Hefei, China

Deyuan Xiao