International Business Machines Corporation

Nova Corporation

Dexin Kong

Kangguo Cheng

Juntao Li

Takashi Ando

Zhenxing Bi

Zheng Xu

Soon-Cheon Seo

Hiroyuki Miyazoe

Youngseok Kim

Daniel Schmidt

Ekmini Anuja De Silva

Joel Pereira De Souza

Babar Ali Khan

Eduard Albert Cartier

Ashim Dutta

Huai Huang

Qianwen Chen

Robin Hsin Kuo Chao

Iqbal Rashid Saraf

Ruilong Xie

Lawrence Alfred Clevenger

Tenko Yamashita

Chen Zhang

Theodorus E Standaert

Shogo Mochizuki

Vijay Narayanan

Muthumanickam Sankarapandian

Paul Charles Jamison

Kevin W Brew

Nicole A Saulnier

Shyng-Tsong Chen

Raghuveer Reddy Patlolla

Jie Yang

Igor Turovets

Aron Cepler

Mary Breton

Marjorie Cheng

Roy Koret

A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.

Redundant bottom pad and sacrificial via contact for process induced RRAM forming

Semiconductor devices and methods for forming the semiconductor devices are described. An example semiconductor structure can include a substrate including a first electrode. The example semiconductor structure can further include a heater element directly contacting the first electrode in the substrate. The example semiconductor structure a phase change cell directly on the heater element. The sidewalls of the phase change cell can be encapsulated with a spacer. The example semiconductor structure a second electrode directly on the phase change cell and the spacer.

Phase change memory with encapsulated phase change element

A resistive RAM module comprises a source electrode and an intermediate electrode that is formed on the source electrode. The intermediate electrode has a closed-curve profile. The resistive RAM module also comprises a memristor element that is deposited on the intermediate electrode. The resistive RAM module also comprises a sink electrode that is in contact with the memristor element. The intermediate electrode is electrically between the source electrode and the memristor element and the memristor element is electrically between the intermediate electrode and the sink electrode.

ReRAM module with intermediate electrode

A phase change memory (PCM) device is provided. The PCM device includes a bottom electrode formed on a substrate, a heater electrode formed on the bottom electrode, the heater electrode having a tapered portion that becomes narrower in a direction away from the substrate. The PCM device also includes an interlayer dielectric (ILD) layer formed on the tapered portion of the heater electrode, the interlayer layer dielectric including an airgap that at least partially surrounds the tapered portion of the heater electrode. The PCM device also includes a phase change layer formed on the heater electrode, and a top electrode formed on the phase change layer.

PCM cell with nanoheater surrounded with airgaps

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Oxide-based resistive memory having a plasma-exposed bottom electrode

A method, a system, and a non-transitory computer readable medium for measuring a local critical dimension uniformity of an array of two-dimensional structural elements, the method may include obtaining an acquired optical spectrometry spectrum of the array; feeding the acquired optical spectrometry spectrum of the array to a trained machine learning process, wherein the trained machine learning process is trained to map an optical spectrometry spectrum to an average critical dimension (CD) and a local critical dimension uniformity (LCDU); and outputting, by the trained machine learning process, the average CD and the LCDU of the array.

Measuring local CD uniformity using scatterometry and machine learning

A method of manufacturing a semiconducting device that includes forming first opening for forming bottom electrode hole in a first area of a semiconductor wafer; forming a deeper second opening for overlay/alignment hole in second area; depositing a bottom electrode metal layer filling the first opening to form a bottom electrode and partially filling the second opening. A layer of sacrificial material is then deposited above the bottom electrode layer and completely filling the second opening. A chemical-mechanical planarization process is performed to remove the -bottom electrode metal and -sacrificial layer, the -sacrificial material layer being removed above a surface defined atop the filled remaining portion above the second opening. The sacrificial layer material is removed in the remaining portion of the second opening. The second opening providing an overlay/alignment feature topography detectable for alignment by lithography and for overlay measurement on the overlay metrology tool.

Maskless alignment scheme for BEOL memory array manufacturing

A neural network device comprises a first plurality of synapse network capacitors, wherein the synapse network capacitors of the first plurality of synapse network capacitors share a first output terminal. The neural network device further comprises a second plurality of synapse network capacitors, wherein the synapse network capacitors of the second plurality of synapse network capacitors share a second output terminal. Still further, the neural network device comprises a metal shielding disposed between the first output terminal and the second output terminal. The neural network device may be used as part of an artificial intelligence system.

Capacitor-based synapse network structure with metal shielding between outputs

Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

BEOL fat wire level ground rule compatible embedded artificial intelligence integration

A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.

Confining filament at pillar center for memory devices

Methods of forming a settable resistance device, settable resistance devices, and neuromorphic computing devices include isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor layer, to selectively form divots in exposed sidewalls of the conductor layer. The stack of layers is isotropically etched to selectively form divots in exposed sidewalls of the insulator layer, thereby forming a tip at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the stack of layers to cover the tip. An electrode is formed over the dielectric layer, such that the dielectric layer is between the electrode and the tip.

Nanotip filament confinement

A high-density resistive random-access memory array with self-aligned bottom electrode contact includes a plurality of electrically conductive structures embedded in an interconnect dielectric material layer, a bottom electrode selectively grown over, and electrically connected to, each of the electrically conductive structures with the bottom electrode above an electrically conductive structure being separated from the bottom electrode above another electrically conductive structure by a first dielectric filling layer, the bottom electrode having a semi-circular shape. The array further includes a resistive random-access memory pillar disposed above the bottom electrode.

High-density resistive random-access memory array with self-aligned bottom electrode contact

Embodiments disclosed herein include an RRAM cell. The RRAM cell may include a first nanowire electrically connected to a first wordline electrode. The nanowire may include a first sharpened point distal from the first wordline electrode. The RRAM cell may also include a metal contact electrically connected to a bitline electrode and a high-&#x3ba; dielectric layer directly between the nanowire and the metal contact.

Filament confinement in resistive random access memory

A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.

Embedded memory pillar

A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

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Guilderland, NY, United States of America

Dexin Kong