Marvell Asia Pte., Ltd.

Delta Electronics Int'l (singapore) Pte Ltd

Devrishi Khanna

Kai Wu

Chirn Chye Boon

Jack Sheng Kee

Kaituo Yang

Lei Mei

Sheung Yan Simon Ng

Kok Hin Teng

Write apparatus for a disk drive includes a write head, write current circuitry connected to the write head for generating a steady-state write current, overshoot current circuitry connected to the write head for generating write current overshoot pulses, and a T-coil termination network between (a) the write current circuitry and the overshoot current circuitry, and (b) a first node connected to a first input of a transmission line together with the write head. The T-coil termination network may include a first inductor connected to the first node, a second inductor coupled with the first inductor at a second node, and a first termination resistor between the first inductor and a common voltage. An output of the overshoot current circuitry may be connected to the first node, and an output of the write current circuitry may be connected to the second node.

Bridged T-coil for increased bandwidth in hard disk drive write circuitry

A data delay circuit, for delaying a portion of a data signal for application to a write head of a hard disk drive, includes a data delay cell including two inverters and a charge current source for charging at least one of the inverters, and a bias circuit for programming delay of the data delay cell. The bias circuit is in current-mirroring relationship with the charge current source and includes a current-based digital-to-analog converter (DAC) for programmably selecting the delay of the data delay cell, and a reference current source for the DAC. The data delay cell and the bias circuit are subject to gain error, and the data delay circuit further includes compensation circuitry for reducing the effect of the gain error. The compensation circuitry may include replica charge current and reference current sources that are fed back through a gain cell.

Data delay cell for rise time programming in write preamplifier

A charge-based charge pump with wide output voltage range is provided. In the charge-based charge pump, the digital logic circuit is configured to receive an up pulse signal and a down pulse signal and output a plurality of switching signals for controlling the first NMOS, the positive hold subcircuit, the first dynamic body-bias generator, the positive charge transfer subcircuit, the first static body-bias generator, the first PMOS, the negative hold subcircuit, the second dynamic body-bias generator, the negative charge transfer subcircuit and the second static body-bias generator electrically connected therewith, so as to allow the output voltage to range from &#x2212;0.84&#xb7;VDD to 1.82&#xb7;VDD. The charge-based charge pump is triggered by the up or down pulse signal or works in a default state, and the top plate and the bottom plate of the pump capacitor are electrically connected to different node and terminal according to the plurality of switching signals.

Charge-based charge pump with wide output voltage range

A low noise amplifier is provided. The low noise amplifier includes an input port, an output port, an inverter, a plurality of switched-capacitor units and a feedback inductor. The inverter is electrically connected between the input port and the output port. Each of the plural switched-capacitor units is electrically connected with the inverter in parallel and includes a switch and a capacitor connected in series. The feedback inductor is electrically connected with the inverter in parallel.

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Singapore, Singapore

Devrishi Khanna