Texas Instruments Corporation

Devraj Matharampallil Rajagopal

Srikanth Srinivasan

Jhankar Malakar

Rajat Chauhan

Nitesh Mishra

Samiran Dasgupta

Yash Didhe

Likhita Chandrashekara

Bharat Gajanan Hegde

Pranshu Kalra

Rajagopalan P

Rajagopalan Parthasarathy

One example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.

Ultra-low power, high speed poly fuse eprom

An integrated circuit. The integrated circuit includes: (i) a clocked circuit operable in response to a clock; (ii) a clock providing circuit, coupled to clock the clocked circuit at a selectable frequency; (iii) a test circuit coupled to the clock providing circuit and the clocked circuit; and (iv) a pad configured to receive an external signal, wherein the selectable frequency is selected in response to the external signal.

High speed integrated circuit testing

An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.

Robust noise immune, low-skew, pulse width retainable glitch-filter

A receiver includes a low-side buffer having an input terminal coupled to receive an input signal and having an output terminal coupled to a buffer terminal. Responsive to the input signal being LOW, the low-side buffer is configured to couple the buffer terminal to ground. The receiver also includes a high-side buffer having an input terminal coupled to receive the input signal and having an output terminal coupled to the buffer terminal. Responsive to the input signal being HIGH, the high-side buffer is configured to provide an I/O voltage at the buffer terminal. The receiver also includes an output stage coupled to the buffer terminal and having a low voltage terminal configured to receive a low supply voltage. The output stage is configured to provide an output signal responsive to the I/O voltage at the buffer terminal, wherein the output signal is lower than the I/O voltage.

Input buffer with wide range of I/O voltage level

An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switches to the feedback switches to accelerate the pull up or the pull down.

A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

Failsafe device

A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.

Failsafe, ultra-wide voltage input output interface using low-voltage gate oxide transistors

An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.

Technique to realize high voltage IO driver in a low voltage BiCMOS process

An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

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Bengaluru, India

Devraj Matharampallil Rajagopal