Juniper Networks, Inc.

DeviPrasad Natesan

Meenakshi S Subramanian

Charles Frederick Barry

Feng Frank Pan

Philip Kruzinski

David R Jorgensen

Tian (Alan) Shen

Murthy Garikiparthi

Guochun (George) Zhao

James Michael Murphy

Abhijit Kumar Choudhury

Tian Shen

Guochun George Zhao

Keith Eric Holleman

Guochun Zhao

In one example, a network controller manages a network having many network devices. Network devices can receive the timing flow port role assignments from the network controller based on the controller's global view of the network topology. The controller can also calculate timing offsets to be applied to the network devices, based on timestamp information obtained by the network devices via exchanging time synchronization protocol messages, and the controller can update time clocks on all of the network devices within a single window of time, based on a timing offsets calculated in single iteration of calculations.

Controller-based network device timing synchronization

An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values

In one example, network device includes a control unit having one or more hardware-based microprocessors and an interface. The interface can receive a first time synchronization message from a master device that comprises a first TTL value. The first TTL value can be indicative of a number of hops traversed by the first time synchronization message. The interface can subsequently receive a second time synchronization message from the master device that comprises a second TTL value that is is indicative of a number of hops traversed by the second time synchronization message. The network device can also include a timing module that determines a time adjustment based at least in part on the determination that the first and second TTL values are different, and applies the time adjustment to update the time of the network device.

Time adjustment using time-to-live values

An apparatus and method of scheduling timing packets to enhance time distribution includes an improved apparatus in a system in which at least one of time and frequency information is derived based on information distributed in timing packets, at least some of the timing packets being transmitted by or received by the apparatus. The improvement includes a scheduling module that determines a first packet transmission time offset of a first timing packet based on a first predetermined identifier associated with the apparatus, and a second packet transmission time offset of a second timing packet based on the first packet transmission time offset and a timing packet spacing that is independent of the first predetermined identifier. The improvement further includes a transmission module that transmits the first timing packet based on the first packet transmission time offset, and the second timing packet based on the second packet transmission time offset.

Apparatus and method of scheduling timing packets to enhance time distribution in telecommunication networks

An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

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Sunnyvale, CA, United States of America

DeviPrasad Natesan