Micron Technology Incorporated

Devin M Batutis

Kishore Kumar Muchherla

Xiangang Luo

Mustafa Nazmi Kaynak

Shane G Nowell

Sivagnanam Parthasarathy

Peter Sean Feeley

Sampath K Ratnam

Karl David Schuh

Jiangang Wu

Harish Reddy Singidi

Preston Allen Thomson

Scott Anthony Stoller

Giuseppe Cariello

Ting Luo

Deping He

Kulachet Tanpairoj

Chun Sum Yeung

Avinash Rajagiri

Pitamber Shukla

Sheng-Huang Lee

Ching-Huang Lu

Andrei Mihnea

Jeffrey Alan Kessenich

Mastafa N Kaynak

An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

Voltage bin calibration based on a voltage distribution reference voltage

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

Managing error-handling flows in memory devices

Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

Memory operation based on block-associated temperature

Prioritization of Vscans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of Vscans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.

Dynamic prioritization of selector Vscans

A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

Voltage calibration scans to reduce memory device overhead

Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.

Selective partitioning of sets of pages programmed to memory device

A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

Managing workload of programming sets of pages to memory device

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.

A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.

Voltage bin calibration based on a temporary voltage shift offset

A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

Multi-tier threshold voltage offset bin calibration

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.

A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.

A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device is to perform operations, including receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The operations further include partitioning the set of pages into a set of partitions, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.

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San Jose, CA, United States of America

Devin M Batutis