Globespan Virata Corporation

Menara Networks, Inc.

Devin K Ng

Salam Elahmadi

Brian Horng

John M Ross

Harry Tan

Benedict A Itri

Jomo K Edwards

Christopher A Gill

James J Zhao

Matthias Bussman

An embodiment of the present invention is a technique for timing recovery. A frequency acquisition loop locks a voltage controlled oscillator (VCO) clock of a multi-band VCO to a reference clock. The frequency acquisition loop generates first and second feedback clocks from the VCO clock. A data lock phase loop generates a driving signal corresponding to a phase error signal from interleaved partial response signal (PRS) samples based on the second feedback clock. The driving signal controls the multi-band VCO in a data phase lock mode. A lock detect controller detects a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock.

Timing recovery for partial-response maximum likelihood sequence detector

A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.

Filter tuner system and method

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Mission Viejo, CA, United States of America

Devin K Ng