International Business Machines Corporation

Devika Sil

Alexander Reznicek

Oleg Gluschenkov

Takeshi Nogami

Benjamin David Briggs

Yasir Sulehria

Daniel C Edelstein

Son Van Nguyen

Alfred Grill

Christian Lavoie

Yann Mignot

Hosadurga K Shobha

Nicholas Anthony Lanzillo

Ashim Dutta

Donald Francis Canaperi

Cornelius Brown Peethala

John Christopher Arnold

Huai Huang

James John Kelly

Thomas J Haigh, Jr

Balasubramanian S Pranatharthi Haran

Huy Cao

Prasad Bhosale

Kedari Matam

Han You

A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Embedded metal contamination removal from BEOL wafers

A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Forming high carbon content flowable dielectric film with low processing damage

Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.

Large grain copper interconnect lines for MRAM

An integrated circuit (IC) structure includes a dielectric layer extending along a first axis to define a length and a second axis orthogonal to the first axis to define a width. A dual-metal via is embedded in the dielectric layer. The dual-metal via includes via sidewalls surrounding a via core. An electrically conductive line extends along the first axis and on an upper surface of the dual-metal via. A side portion of the via core is co-planar with a sidewall of the electrically conductive line.

Interconnects including dual-metal vias

A harden gap fill dielectric material that has improved chemical and physical properties is formed laterally adjacent to a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode structure of a memory structure. The harden gap fill dielectric material can be formed by introducing, via ion implantation, a bond breaking additive into an as deposited gap fill dielectric material layer and thereafter curing the gap fill dielectric material layer containing the bond breaking additive. The curing includes UV curing alone, or UV curing in combination with laser annealing. The curing employed in the present application does not negatively impact the MTJ pillar or top electrode structure.

MRAM devices containing a harden gap fill dielectric material

The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Interconnect with self-forming wrap-all-around barrier layer

Growing community of inventors

Rensselaer, NY, United States of America

Devika Sil