International Business Machines Corporation

Devika Sarkar Grant

Ruilong Xie

Son Van Nguyen

Michael Rizzolo

Sagarika Mukesh

Fee Li Lie

Kisik Choi

Hosadurga K Shobha

Somnath Ghosh

Nikhil Jain

Prabudhya Roy Chowdhury

Gauri V Karve

Thamarai Selvi Devarajan

Shravan Kumar Matham

Aakrati Jain

According to the embodiment of the present invention, a semiconductor device includes a first source/drain and a second source/drain. A first source/drain contact includes a first portion and a second portion. The first portion of the first source/drain contact is located directly atop the first source/drain. The second portion of the first source/drain contact extends vertically past the first source/drain. The first source/drain is in direct contact with three different sides of a first section of the second portion of the first source/drain contact.

Via to backside power rail through active region

One or more systems, devices and/or methods provided herein relate to a circuit device having a modular or selectively designed interconnect structure with a plurality of conformal features. In the semiconductor realm, such achievements can allow for fabrication of a device with sub 18 nanometer (nm) or lesser pitch between adjacent and/or parallel lines of the interconnect structure. A device can comprise a semiconductor device having an interconnect structure having a first set of parallel lines and a second set of parallel lines, where the lines of the first set can be arranged in a transverse direction to the lines of the second set. The lines of the first set can be disposed orthogonally to the lines of the second set. The first second sets of lines can comprise first and second rounded jogs that are conformal to one another and which connect the first set of lines to the second set of lines.

Circuit interconnect structure

Embodiments herein include semiconductor structures with a first source/drain (S/D) connected to a first field-effect transistor (FET) region, a second S/D connected to a second FET region, and a buried power rail (BPR) region. The BPR region may include a BPR, a first dielectric liner lining a first lateral side of the BPR region, and a second dielectric liner lining a second lateral side. The first dielectric liner isolates the BPR from the first FET region and the first S/D, and the second dielectric liner isolates the BPR from the second FET region. Embodiments may also include a contact electrically connecting the second S/D and the BPR through a second lateral side of the BPR region. The liners enable the BPR to be formed after the formation of gates and the S/Ds, so that the BPR does not cause problems during annealing processes of the gates and the S/Ds.

Buried power rail after replacement metal gate

A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Multilayer dielectric stack for damascene top-via integration

Provided is a semiconductor device. The semiconductor device comprises a transistor comprising a plurality of source/drain epitaxies. The semiconductor device further comprises at least one backside power rail under the transistor. The semiconductor device further comprises a backside inter-layer dielectric (ILD) located between the plurality of source/drain epitaxies and the at least one power rail. The semiconductor device further comprises a first backside contact connecting a first source/drain epitaxy to the at least one backside power rail. The semiconductor device further comprises one or more contact placeholders formed under the other source/drain epitaxies.

Self-aligned backside contact integration for transistors

A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

High aspect ratio buried power rail metallization

Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.

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Rensselaer, NY, United States of America

Devika Sarkar Grant