Micron Technology Incorporated

Devesh Dadhich Shreeram

Sanjeev Sapra

Sevim Korkmaz

Kangle Li

Matthew N Rocklein

Jerome A Imonigie

Diem Thy N Tran

Dewali Ray

Paul A Paduano

Scott E Sills

Jian Li

Si-Woo Lee

Christopher W Petz

Irina V Vasilyeva

Silvia Borsari

Yi Fang Lee

Christopher J Gambee

Mohd Kamran Akhtar

Guangjun Yang

Vinay Nair

Darwin Franseda Fan

Zhiqiang Xie

Gurpreet S Lugani

Masihhur R Laskar

Sanket S Kelkar

An-Jen B Cheng

Yoshitaka Nakamura

Ashwin Panday

Srinivasan Balakrishnan

Kaustubh Shrimali

Ping-Cheng Hsu

Wei Ching Huang

Methods, apparatuses, and systems related to an over-sculpted storage node are described. An example method includes forming an opening in a pattern of materials. The method further includes performing an etch to over-sculpt the opening. The method further includes depositing a storage node material in the over-sculpted opening to form an over-sculpted storage node. The method further includes performing an etch to remove portions of the pattern of materials. The method further includes performing an etch on the storage node material to trim the over-sculpted storage node.

Over-sculpted storage node

A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.

Capacitors with electrodes having a portion of material removed, and related semiconductor devices, systems, and methods

Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.

Integrated assemblies and methods of forming integrated assemblies

Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Integrated memory with redistribution of capacitor connections, and methods of forming integrated memory

Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.

Column formation using sacrificial material

Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.

Semiconductor structure patterning

Methods, apparatuses, and systems related to forming a capacitor using a hard mask material are described. An example method includes patterning a surface to have a first silicate material, a first nitride material on the first silicate material, a second silicate material on the first nitride material, a second nitride material on the second silicate material, and a sacrificial material on the second nitride material. The method further includes forming a hard mask material on the sacrificial material. The method further includes forming a capacitor material in an opening through the first silicate material, the first nitride material, the second silicate material, the second nitride material, the sacrificial material, and the hard mask material. The method further includes removing the sacrificial material and the hard mask material.

Formation of a capacitor using a hard mask

Methods, apparatuses, and systems related to forming a capacitor using a sacrificial material are described. An example method includes forming a first silicate material on a substrate. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes forming a column of capacitor material through the first silicate material, the first nitride material, the second silicate material, the second nitride material, and the sacrificial material. The method further includes removing the sacrificial material to expose a top portion of the capacitor material.

Formation of a capacitor using a sacrificial layer

Methods, apparatuses, and systems related to reduction of roughness on a sidewall of an opening are described. An example method includes forming a liner material on a first sidewall of an opening in a first silicate material and on a second sidewall of the opening in an overlying second silicate material, where the liner material is formed to a thickness that covers a roughness on the first sidewall extending into the opening. The example method further includes removing the liner material from the first sidewall of the opening and the second sidewall of the opening with a non-selective etch chemistry to reduce the roughness on the first sidewall.

Reduction of roughness on a sidewall of an opening

Methods, apparatuses, and systems related to shaping a storage node material are described. An example method includes forming a pillar with a pattern of materials. The method further includes depositing a storage node material on a side of the pillar. The method further includes etching sacrificial materials within the pillar. The method further includes etching the storage node material in a direction from the pillar into the storage node.

Storage node shaping

Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.

Semiconductor structure formation

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Boise, ID, United States of America

Devesh Dadhich Shreeram